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參數(shù)資料
| 型號(hào)： | AD5306BRUZ-REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD W/BUFF 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 4.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 167k |
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AD5306/AD5316/AD5326
Rev. F | Page 15 of 24
FUNCTIONAL DESCRIPTION
The AD5306/AD5316/AD5326 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains four output buffer amplifiers
and is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each
DAC is provided with a separate reference input, which can be
buffered to draw virtually no current from the reference source,
or unbuffered to give a reference input range from 0.25 V to
VDD. The devices have a power-down mode in which all DACs
can be turned off completely with a high impedance output.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
VREF pin provides the reference voltage for the corresponding
DAC. Figure 29 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
N
REF
OUT
D
V
2
×
=
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for AD5306 (8 bits)
0 to 1023 for AD5316 (10 bits)
0 to 4095 for AD5326 (12 bits)
N is the DAC resolution.
INPUT
REGISTER
OUTPUT BUFFER
AMPLIFIER
REFERENCE
BUFFER
VOUTA
VREFA
BUF
RESISTOR
STRING
DAC
REGISTER
02066-029
Figure 29. Single DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
DAC REFERENCE INPUTS
Each of the four DACs has a reference pin. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as 0.25 V and as high as VDD, since there is no
restriction due to headroom and footroom of the reference
amplifier.
R
TO OUTPUT
AMPLIFIER
02066-030
Figure 30. Resistor String
If there is a buffered reference in the circuit (for example,
REF192), there is no need to use the on-chip buffers of the
AD5306/AD5316/AD5326. In unbuffered mode, the input
impedance is still large at typically 180 kΩ per reference input
for 0 V to VREF mode and 90 kΩ for 0 V to 2 VREF mode.
The buffered/unbuffered option is controlled by the BUF bit in
the control byte. The BUF bit setting applies to whichever DAC
is selected in the pointer byte.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, GAIN, offset error, and gain error. If a gain
of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. Because of clamping, however, the maximum output
is limited to VDD – 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to
GND or VDD in parallel with 500 pF to GND or VDD. The source
and sink capabilities of the output amplifier can be seen in the
plot in Figure 16.
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at eight bits) of 6 μs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5306BRUZ-REEL71 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2.5 V to 5.5 V, 400 ??A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs |
| AD5307 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| AD53071-01 | 制造商:Analog Devices 功能描述: |
| AD5307ARU | 制造商:Analog Devices 功能描述:DAC 4-CH Resistor-String 8-bit 16-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:8-BIT QUAD DAC I.C. - Bulk |
| AD5307ARU-REEL7 | 制造商:Analog Devices 功能描述:DAC 4-CH Resistor-String 8-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 4-CH RES-STRING 8BIT 16TSSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:8-BIT QUAD DAC I.C. - Tape and Reel |
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