- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373876 > AD5300 (Analog Devices, Inc.) Rail-to-Rail Voltage Output 8-Bit DAC(滿幅度電壓輸出8位D/A轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | AD5300 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail Voltage Output 8-Bit DAC(滿幅度電壓輸出8位D/A轉(zhuǎn)換器) |
| 中文描述： | 軌至軌電壓輸出的8位DAC（滿幅度電壓輸出8位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AD5300 |
AD5300
–9–
REV. 0
SYNC
Interrupt
In a normal write sequence, the
SYNC
line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if
SYNC
is brought high before the
16th falling edge this acts as an interrupt to the write sequence.
T he shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 23.
Power-On-Reset
T he AD5300 contains a power-on-reset circuit which controls
the output voltage during power-up. T he DAC register is filled
with zeros and the output voltage is 0 V. It remains there until
a valid write sequence is made to the DAC. T his is useful in
applications where it is important to know the state of the out-
put of the DAC while it is in the process of powering up.
Power-Down Modes
T he AD5300 contains four separate modes of operation. T hese
modes are software-programmable by setting two bits (DB13
and DB12) in the control register. T able I shows how the state
of the bits corresponds to the mode of operation of the device.
T able I. Modes of Operation for the AD5300
DB13
DB12
Operating Mode
0
0
Normal Operation
Power-Down Modes
1 k
to GND
100 k
to GND
T hree-State
0
1
1
1
0
1
When both bits are set to 0, the part works normally with its
normal power consumption of 140
μ
A at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. T his has the
advantage that the output impedance of the part is known while
the part is in power-down mode. T here are three different options.
T he output is connected internally to GND through a 1 k
resis-
tor, a 100 k
resistor or it is left open-circuited (T hree-State).
T he output stage is illustrated in Figure 24.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
Figure 24. Output Stage During Power-Down
T he bias generator, the output amplifier, the resistor string and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. T he time to
exit power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s for
V
DD
= 3 V. See Figure 18 for a plot.
MICROPROCE SSOR INT E RFACING
AD5300 to ADSP-2101/ADSP-2103 Interface
Figure 25 shows a serial interface between the AD5300 and the
ADSP-2101/ADSP-2103. T he ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT T ransmit Alternate Framing
Mode. T he ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: Internal Clock Operation, Active Low Framing, 16-
Bit Word Length. T ransmission is initiated by writing a word to
the T x register after the SPORT has been enabled.
SCLK
ADSP-2101/
ADSP-2103*
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
SCLK
AD5300*
TFS
Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface
DB15
DB0
SCLK
SYNC
DIN
DB15
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
INVALID WRITE SEQUENCE:
SYNC
HIGH BEFORE 16
TH
FALLING EDGE
Figure 23.
SYNC
Interrupt Facility
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD53032JSTP | Silver Mica Capacitor; Capacitance:12pF; Capacitance Tolerance:+/- 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| AD53032 | High Performance Driver/Comparator Active Load on a Single Chip |
| AD53033 | High Performance Driver/Comparator on a Single Chip |
| AD53033JSTP | High Performance Driver/Comparator on a Single Chip |
| AD53040KRP | Ultrahigh Speed Pin Driver with Inhibit Mode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD53000-2 | 制造商:Analog Devices 功能描述:53000-2 |
| AD53000-3 | 制造商:Analog Devices 功能描述:53000-3 |
| ad53000p-reel | 制造商:Analog Devices 功能描述: |
| AD53000-REEL | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。