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參數(shù)資料
| 型號(hào)： | AD5300 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail Voltage Output 8-Bit DAC(滿幅度電壓輸出8位D/A轉(zhuǎn)換器) |
| 中文描述： | 軌至軌電壓輸出的8位DAC（滿幅度電壓輸出8位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 221K |
| 代理商： | AD5300 |
AD5300
–4–
REV. 0
PIN CONFIGURAT IONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
OUT
GND
V
DD
SYNC
SCLK
DIN
AD5300
SOT-23
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
NC
AD5300
m
SOIC
SYNC
V
OUT
GND
V
DD
SCLK
DIN
NC
SOT -23
m
SOIC
NC = NO CONNECT
PIN FUNCT ION DE SCRIPT IONS
SOT -23 Pin Numbers
Pin
No.
Mnemonic
Function
1
2
3
V
OUT
GND
V
DD
Analog output voltage from DAC. T he output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Power Supply Input. T hese parts can be operated from +2.5 V to +5.5 V and should be decoupled
to GND.
Serial Data Input. T his device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level triggered control input (active low). T his is the frame synchronization signal for the input
data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. T he DAC is updated following the 16th clock cycle unless
SYNC
is taken high before this edge in which case the rising edge of
SYNC
acts as an interrupt and
the write signal is ignored by the DAC.
4
DIN
5
SCLK
6
SYNC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD53000-2 | 制造商:Analog Devices 功能描述:53000-2 |
| AD53000-3 | 制造商:Analog Devices 功能描述:53000-3 |
| ad53000p-reel | 制造商:Analog Devices 功能描述: |
| AD53000-REEL | 制造商:Analog Devices 功能描述: |
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