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參數(shù)資料
| 型號： | AD5293BRUZ-100-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 1024POS 100K 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 1024 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線串行 |
| 電源電壓： | 9 V ~ 33 V，±9 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
AD5293
Rev. D | Page 21 of 24
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B terminal and wiper-to-A terminal that is proportional
to the input voltage at A to B, as shown in Figure 48. Unlike the
polarity of VDD to GND, which must be positive, voltage across
A to B, W to A, and W to B can be at either polarity.
07
67
5-
0
42
W
A
B
VIN
VOUT
Figure 48. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity,
connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B that
ranges from 0 V to 30 V 1 LSB. Each LSB of voltage is equal to
the voltage applied across the A terminal and B terminal, divided
by the 1024 positions of the potentiometer divider. The general
equation defining the output voltage at VW, with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B, is
B
A
W
V
D
V
D
V
×
+
×
=
1024
)
(
(3)
To optimize the wiper position update rate when in voltage
divider mode, it is recommended that the internal ±1% resistor
tolerance calibration feature be disabled by programming Bit C2
of the control register (see Table 11).
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, RWA and RWB, and not on the absolute
values. Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 μF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 49) on power-up and throughout the operation
of the AD5293. This capacitor must have a voltage rating of ≥7 V.
AD5293
GND
C1
1F
EXT_CAP
07
67
5-
04
3
Figure 49. Hardware Setup for the EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5293
define the boundary conditions for proper 3-terminal, digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed VDD or VSS are clamped by the
internal forward-biased diodes (see Figure 50).
VSS
VDD
A
W
B
07
67
5-
04
4
Figure 50. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5293 is primarily used as a digital
ground reference. To minimize the digital ground bounce, the
AD5293 ground pin should be joined remotely to common ground.
The digital input control signals to the AD5293 must be referenced
to the device ground pin (GND) to satisfy the logic level defined
in the Specifications section.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (see Figure 50), it is important to power
VDD and VSS first, before applying any voltage to the A, B, and W
terminals. Otherwise, the diode is forward-biased such that VDD
and VSS are powered up unintentionally. The ideal power-up
sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then
VA, VB, and VW. The order of powering up VA, VB, VW, and the
digital inputs is not important, as long as they are powered after
VDD, VSS, and VLOGIC.
Regardless of the power-up sequence and the ramp rates of the
power supplies, the power-on preset activates after VLOGIC is
powered, restoring midscale to the RDAC register.
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