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參數(shù)資料
| 型號： | AD5290YRMZ50-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Compact +30V/【15V 256-Position Digital Potentiometer |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | LEAD FREE, MO-187-BA, MSOP-10 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 150K |
| 代理商： | AD5290YRMZ50-RL7 |
Preliminary Technical Data
AD5290
TIMING CHARACTERISTICS— 10 k, 50 k, 100 k VERSIONS
(V
DD
/V
SS
= ±15V±10% or ±5V±10%, V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +105°C unless otherwise noted.)
Table 2.
Parameter
Symbol
SPI INTERFACE TIMING CHARACTERISTICS
6, 8,9
(Specifications Apply to All Parts)
Clock Frequency
f
CLK
Input Clock Pulsewidth
t
CH
, t
CL
Data Setup Time
t
DS
Data Hold Time
t
DH
CLK to SDO Propagation Delay
t
PD
Rev. Pr C | Page 4 of 11
Conditions
Min
Typ
1
Max
4
100
Unit
MHz
ns
ns
ns
ns
Clock level high or low
R
PU
= 1K
, C
L
< 20pF
120
30
20
10
NOTES
1.
2.
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
t
CSS
t
CSW
t
CSH0
t
CSH1
t
CS1
120
150
TBD
120
120
ns
ns
ns
ns
ns
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
AB
= V
DD
, Wiper (V
W
) = no connect.
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
=V
DD
and V
B
=0 V.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
P
DISS
is calculated from (I
DD
× V
DD
+ I
SS
× V
SS
) CMOS logic level inputs result in minimum power dissipation.
All dynamic characteristics use V
DD
/ V
SS
= ±5 V.
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V.
3.
4.
5.
6.
7.
8.
9.
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