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參數(shù)資料
| 型號： | AD526 |
| 英文描述： | Software Programmable Gain Amplifier |
| 中文描述： | 軟件可編程增益放大器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 464K |
| 代理商： | AD526 |
AD526
REV. D
–10–
GROUNDING AND BYPASSING
Proper signal and grounding techniques must be applied in
board layout so that specified performance levels of precision
data acquisition components, such as the AD526, are not
degraded.
As is shown in Figure 37, logic and signal grounds should be
separate. By connecting the signal source ground locally to the
AD526 analog ground Pins 5 and 6, gain accuracy of the
AD526 is maintained. This ground connection should not be
corrupted by currents associated with other elements within the
system.
GAIN
NETWORK
LATCHES AND LOGIC
DIGITAL
GROUND
AMP
V
OUT
FORCE
V
OUT
SENSE
ANALOG
GROUND 1
ANALOG
GROUND 2
+V
S
–V
S
AD526
V
IN
+15V
–15V
0.1
m
F
0.1
m
F
0.1
m
F
0.1
m
F
1
m
F
+5V
AD574
12-BIT
A/D
CONVERTER
Figure 37. Grounding and Bypassing
OUT
FORCE
OUT
SENSE
0.1
m
F
–V
S
0.1
m
F
+V
S
+5V
A2
A1
A0
V
IN
CLK
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
–
AD526
16
8
4
2
1
GAIN NETWORK
A1
A0
LOGIC AND LATCHES
CS
CLK
A2
B
OUT
FORCE
OUT
SENSE
V
OUT
0.1
m
F
–V
S
0.1
m
F
+V
S
+5V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
–
AD526
16
8
4
2
1
GAIN NETWORK
A1
A0
LOGIC AND LATCHES
CS
CLK
A2
B
Figure 38. Cascaded Operation
Utilizing the force and sense outputs of the AD526, as shown in
Figure 38, avoids signal drops along etch runs to low impedance
loads.
Table II. Logic Table for Figure 38
V
OUT
/V
IN
1
2
4
8
16
32
64
128
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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| AD526BD | Software Programmable Gain Amplifier |
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