- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362090 > AD524BD (ANALOG DEVICES INC) Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier PDF資料下載
參數(shù)資料
| 型號(hào)： | AD524BD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 100 uV OFFSET-MAX, 1 MHz BAND WIDTH, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 364K |
| 代理商： | AD524BD |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
REV. A
–11–
AD5241/AD5242
bits are O
2
and O
1
. They are extra programmable logic out-
put that users can use to drive other digital loads, logic gates,
LED drivers, and analog switches, etc. The three LSBs are
DON
’
T CARE. See Figure 2.
3. After acknowledging the Instruction Byte, the last byte in
Write mode is the Data Byte, Frame 3. Data is transmitted
over the serial bus in sequences of nine clock pulses (eight
data bits followed by an
“
Acknowledge
”
bit). The transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL, Figure 2.
4. Unlike the Write mode, the Data Byte follows immediately
after the acknowledgment of the Slave Address Byte in the
Read mode, Frame 2. Data is transmitted over the serial bus
in sequences of nine clock pulses (slight difference with the
Write mode, there are eight data bits followed by a
“
No
Acknowledge
”
bit). Similarly, the transitions on the SDA line
must occur during the low period of SCL and remain stable
during the high period of SCL, Figure 3.
5. When all data bits have been read or written, a STOP condition
is established by the master. A STOP condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In Write mode, the master will pull the SDA line high during
the tenth clock pulse to establish a STOP condition (see
Figure 2). In Read mode, the master will issue a No Acknowl-
edge for the ninth clock pulse (i.e., the SDA line remains
high). The master will then bring the SDA line low before
the tenth clock pulse which goes high to establish a STOP
condition (see Figure 3).
A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instruct-
ing the part only once. During the Write cycle, each Data byte
will update the RDAC output. For example, after the RDAC
has acknowledged its Slave Address and Instruction Bytes, the
RDAC output will be updated. If another byte is written to the
RDAC while it is still addressed to a specific slave device with
the same instruction, this byte will update the output of the
selected slave device. If different instructions are needed, the
Write mode has to start a whole new sequence with a new Slave
Address, Instruction, and Data Bytes transferred again. Simi-
larly, a repeated Read function of the RDAC is also allowed.
MULTIPLE DEVICES ON ONE BUS
Figure 5 shows four AD5242 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I
2
C-compatible interface. Note, a device will be addressed
properly only if the bit information of AD0 and AD1 in the
Slave Address Byte matches with the logic inputs at pins AD0
and AD1 of that particular device.
SDA SCL
AD5242
AD1
AD0
SDA
SCL
R
P
R
P
SDA SCL
AD5242
V
DD
AD1
AD0
SDA SCL
AD1
AD0
AD5242
V
DD
SDA SCL
AD5242
V
DD
AD1
AD0
MASTER
5V
Figure 5. Multiple AD5242 Devices on One Bus
LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new
component may be optimized at another. When they operate the
same signal at two different voltages, a proper method of level-
shifting is needed. For instance, one can use a 3.3 V E
2
PROM
to interface with a 5 V digital potentiometer. A level-shift
scheme is needed in order to enable a bidirectional communi-
cation so that the setting of the digital potentiometer can be
stored to and retrieved from the E
2
PROM. Figure 6 shows one
of the techniques. M1 and M2 can be N-Ch FETs 2N7002 or
low threshold FDV301N if V
DD
falls below 2.5 V.
R
P
R
P
S
D
G
M1
S
D
G
M2
3.3V
E
2
PROM
R
P
R
P
5V
AD5242
SCL2
SDA2
V
DD2
= 5V
SCL1
SDA1
V
DD2
= 3.3V
Figure 6. Level-Shift for Different Voltage Devices Operation
IN
1
2
V
DD
O1
V
SS
M
P
M
N
O1 DATA IN FRAME 2
Figure 7. Output Stage of Logic Output O
1
READBACK RDAC VALUE
AD5241/AD5242 allows user to read back the RDAC values in
Read Mode. However, for AD5242 dual channel device, the
channel of interest is the one that is previously selected in Write
Mode. In the case that users need to read the RDAC values of
both channels in AD5242, they can program the first subaddress
in the Write Mode and then change to the Read Mode to read
the first channel value. After that, they can change back to the
Write Mode with the second subaddress and finally read the
second channel value in the Read Mode again. Note that it is
not necessary for users to issue the Frame 3 Data Byte in the
Write Mode for subsequent readback operation. Users should
refer to Figures 2 and 3 for the programming format.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
AD5241/AD5242 features additional programmable logic
outputs, O
1
and O
2
, which can be used to drive digital load,
analog switches, and logic gates. The logic states of O
1
and O
2
can be programmed in Frame 2 of the Write Mode (see Figure 2).
Figure 7 shows the output stage O
1
where the logic levels are
equal to the
supply levels and the current driving capability
reaches tenths of mA.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 8. This applies
to digital input pins SDA, SCL, and
SHDN
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD524BE | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| AD524C | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| AD524CD | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| AD524S | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| AD524SD | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD524BD/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Instrumentation Amp， Pin-Programmable |
| AD524BDZ | 功能描述:IC AMP INST 1MHZ PREC LN 16CDIP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| AD524BE | 功能描述:IC AMP INST 1MHZ PREC LN 20CLCC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| AD524C | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Instrumentation Amplifier |
| AD524CD | 功能描述:IC AMP INST 1MHZ PREC LN 16CDIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 其它有關(guān)文件:TS1854A View All Specifications 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.25 V/µs 增益帶寬積:630kHz -3db帶寬:- 電流 - 輸入偏壓:16nA 電壓 - 輸入偏移:1000µV 電流 - 電源:162µA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。