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參數(shù)資料
| 型號： | AD524BD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 100 uV OFFSET-MAX, 1 MHz BAND WIDTH, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 364K |
| 代理商： | AD524BD |
REV. A
AD5241/AD5242
–10–
D
(DEC)
R
WB
( )
Output State
255
128
1
0
10021
5060
99
60
Full-Scale (R
WB
–
1 LSB + R
W
)
Midscale
1 LSB
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60
is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than
±
20 mA. Otherwise, degradation or possible destruction of
the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled resistance R
WA
. When these terminals are
used, the B terminal can be opened or tied to the wiper termi-
nal. Setting the resistance value for R
WA
starts at a maximum
value of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is:
R
D
( )
=
D
R
R
WA
AB
W
×
+
256
256
–
(2)
For
R
AB
= 10 k
and B terminal can be either open circuit or
tied to W. The following output resistance
R
WA
will be set for
the following RDAC latch codes.
D
(DEC)
R
WA
( )
Output State
255
128
1
0
99
5060
10021
10060
Full-Scale
Midscale
1 LSB
Zero-Scale
The typical distribution of the nominal resistance R
AB
from
channel-to-channel matches within
±
1% for AD5242. Device-
to-device matching is process lot dependent and it is possible to
have
±
30% variation. Since the resistance element is processed
in thin film technology, the change in R
AB
with temperature has
no more than 30 ppm/
°
C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt-
age at A-to-B. Unlike the polarity of V
DD
–
V
SS
, which must be
positive, voltage across A
–
B, W
–
A, and W
–
B can be at either
polarity provided that V
SS
is powered by a negative supply.
If ignoring the effect of the wiper resistance for approximation,
connecting A terminal to 5 V and B terminal to ground pro-
duces an output voltage at the wiper-to-B starting at zero volt
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal AB divided by the 256 position
of the potentiometer divider. Since AD5241/AD5242 can be
supplied by dual supplies, the general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to Terminals A and B is:
V
D
( )
=
DV
256
DV
W
A
B
+
256
256
(3)
which can be simplified to
V
D
( )
=
DV
256
V
W
AB
B
+
(4)
where
D
is decimal equivalent of the binary code between 0 to
255 which is loaded in the 8-bit RDAC register.
For more accurate calculation including the effects of wiper
resistance, V
W
can be found as:
V
D
( )
=
R
D
( )
R
V
R
D
( )
R
V
W
WB
AB
A
WA
AB
B
+
(5)
where
R
WB
(
D
) and
R
WA
(
D
) can be obtained from Equations 1
and 2.
Operation of the digital potentiometer in the divider mode results
in a more accurate operation over temperature. Unlike the rheo-
stat mode, the output voltage is dependent on the ratio of the
internal resistors R
WA
, R
WB
, and not the absolute values; there-
fore, the temperature drift reduces to 5 ppm/
°
C.
DIGITAL INTERFACE
2-Wire Serial Bus
The AD5241/AD5242 are controlled via an I
2
C-compatible
serial bus. The RDACs are connected to this bus as slave devices.
Referring to Figures 2 and 3, the first byte of AD5241/AD5242
is a Slave Address Byte. It has a 7-bit slave address and a R/
W
bit. The 5 MSBs are 01011 and the following two bits are deter-
mined by the state of the AD0 and AD1 pins of the device. AD0
and AD1 allow users to use up to four of these devices on one bus.
The 2-wire I
2
C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high, Figure 2. The following byte is
the Slave Address Byte, Frame 1, which consists of the 7-bit
slave address followed by an R/
W
bit (this bit determines
whether data will be read from or written to the slave device).
The slave whose address corresponds to the transmitted
address will respond by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/
W
bit is high, the master will read
from the slave device. If the R/
W
bit is low, the master will
write to the slave device.
2. A Write operation contains an extra Instruction Byte more
than the Read operation. Such Instruction Byte, Frame 2, in
Write mode follows the Slave Address Byte. The MSB of the
Instruction Byte labeled
A
/B is the RDAC subaddress select.
A
“
low
”
selects RDAC1 and a
“
high
”
selects RDAC2 for the
dual-channel AD5242. Set
A
/B to low for AD5241. The
second MSB, RS, is the Midscale reset. A logic high of this
bit moves the wiper of a selected RDAC to the center tap
where R
WA
= R
WB
. The third MSB, SD, is a shutdown bit. A
logic high on SD causes the RDAC open circuit at Terminal
A while shorting wiper to Terminal B. This operation yields
almost a 0
in rheostat mode or zero volt in potentiometer
mode. This SD bit serves the same function as the
SHDN
pin
except
SHDN
pin reacts to active low. The following two
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