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| 型號(hào)： | AD5172BRM10-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT DUAL OTP 10-MSOP T/R |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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AD5172/AD5173
Data Sheet
Rev. I | Page 18 of 28
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.
LOGIC
340
GND
04103-
030
Figure 43. ESD Protection of Digital Pins
A, B, W
GND
04103-
031
Figure 44. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
boundary conditions for proper 3-terminal digital potenti-
ometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or GND are
clamped by the internal forward-biased diodes (see Figure 45).
GND
A
W
B
VDD
04103-
032
Figure 45. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 45), it
is important to power VDD/GND before applying voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally and
may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, digital inputs, and then VA/VB/VW. The
relative order of powering VA, VB, VW, and the digital inputs is
not important, as long as they are powered after VDD/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
employ fuse link technology that requires 5.6 V to 5.8 V to blow
the internal fuses to achieve a given setting, but normal VDD can
be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation
between the supplies if VDD is lower than the required VDD_OTP.
The fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.6 V to 5.8 V and
must be able to provide a 100 mA transient current for 400 ms
for successful one-time programming. When programming
is completed, the VDD_OTP supply must be removed to allow
normal operation at 2.7 V to 5.5 V; the device consumes only
microamps of current.
VDD
2.7V
5.7V
P1
P1 = P2 = FDV302P, NDS0610
R1
10k
P2
C1
10F
C2
0.1F
APPLY FOR OTP ONLY
AD5172/
AD5173
04103-
035
Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-channel MOSFETs is recom-
mended for the isolation of the supply. As shown in Figure 46,
this assumes that the 2.7 V system voltage is applied first and
that the P1 and P2 gates are pulled to ground, thus turning on
DD_OTP to both the VDD and the
MOSFET gates, thus turning P1 and P2 off. To program the
the OTP command at this time. When the OTP is completed,
or AD5173 is fixed permanently.
internal fuses. Always apply the 5.6 V to 5.8 V one-time pro-
gram voltage requirement at the first fuse programming attempt.
Failure to comply with this requirement may lead to changing
the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD + 0.5 V.
Poor PCB layout introduces parasitics that can affect fuse
programming. Therefore, it is recommended to add a 1 F to
10 F tantalum capacitor in parallel with a 1 nF ceramic capacitor
as close as possible to the VDD pin. The type and value chosen for
both capacitors are important. These capacitors work together to
provide both fast responsiveness and large supply current handling
with minimum supply droop during transients. As a result,
these capacitors increase the OTP programming success by not
inhibiting the proper energy needed to blow the internal fuses.
Additionally, C1 minimizes transient disturbance and low
frequency ripple, whereas C2 reduces high frequency noise
during normal operation.
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