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| 型號： | AD5162BRM2.5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DUAL 2.5K 256POS 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 接片： | 256 |
| 電阻（歐姆）： | 2.5k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 3 線串行（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 配用： | AD5162EVAL-ND - BOARD EVAL FOR AD5162 |
AD5162
Rev. C | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
VI
W
B
VO
04108-0-036
Figure 35. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across the A and B terminals divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
V
256
)
(
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 36 and
Figure 37. This applies to the SDI, CLK, and CS
LOGIC
340
GND
04108-0-037
digital input pins.
Figure 36. ESD Protection of Digital Pins
A, B, W
GND
04108-0-038
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on the A, B, and W terminals that
exceed VDD or GND are clamped by the internal forward-biased
diodes (see Figure 38).
GND
A
W
B
VDD
04108-0-039
Figure 38. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 38), it is important to
power VDD/GND before applying voltage to the A, B, and W
terminals; otherwise, the diode is forward-biased such that VDD
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important, as long as they are powered after VDD/GND.
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