參數(shù)資料
型號: AD5162
廠商: Analog Devices, Inc.
元件分類: 數(shù)字電位計
英文描述: Dual 256-Position SPI Digital Potentiometer
中文描述: 雙256位的SPI數(shù)字電位器
文件頁數(shù): 5/20頁
文件大小: 960K
代理商: AD5162
AD5162
TIMING CHARACTERISTICS—ALL VERSIONS
Table 3. V
DD
= +5 V ± 10%, or +3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; 40°C < T
A
< +125°C; unless otherwise noted
Parameter
Symbol
SPI INTERFACE TIMING CHARACTERISTICS
9
(Specifications Apply to All Parts)
Clock Frequency
f
CLK
Input Clock Pulse Width
t
CH
, t
CL
Data Setup Time
t
DS
Data Hold Time
t
DH
CS Setup Time
t
CSS
CS High Pulse Width
t
CSW
CLK Fall to CS Fall Hold Time
t
CSH0
CLK Fall to CS Rise Hold Time
t
CSH1
CS Rise to Clock Rise Setup
t
CS1
See notes at end of section.
NOTES
Rev. A | Page 5 of 20
Conditions
Min
Typ
1
Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock level high or low
20
5
5
15
40
0
0
10
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (VW) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
9
See timing diagrams for locations of measured values.
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