參數(shù)資料
型號: AD5162
廠商: Analog Devices, Inc.
元件分類: 數(shù)字電位計
英文描述: Dual 256-Position SPI Digital Potentiometer
中文描述: 雙256位的SPI數(shù)字電位器
文件頁數(shù): 14/20頁
文件大?。?/td> 960K
代理商: AD5162
AD5162
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
Rev. A | Page 14 of 20
A
V
I
W
B
V
O
0
Figure 35. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
B
AB
WA
R
A
AB
WB
R
W
V
D
R
V
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures shown in Figure 36 and
Figure 37. This applies to the digital input pins SDI, CLK,
and CS.
LOGIC
340
GND
0
Figure 36. ESD Protection of Digital Pins
A, B, W
GND
0
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND are clamped by the internal forward biased
diodes (see Figure 38).
GND
A
W
B
V
DD
0
Figure 38. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power V
DD
/GND before applying any voltage to terminals A, B,
and W; otherwise, the diode is forward biased such that V
DD
is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
, V
B
, V
W
. The relative order
of powering V
A
, V
B
, V
W
, and the digital inputs is not important
as long as they are powered after V
DD
/GND.
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