參數(shù)資料
型號(hào)： AD5112BCPZ80-500R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/28頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 64POS 80K 8LFCSP
標(biāo)準(zhǔn)包裝： 1
接片： 64
電阻（歐姆）： 80k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C，2 線串口
電源電壓： 1.8 V ~ 5 V，2.3 V ~ 5.5V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-UFDFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 8-LFCSP-UD（2x2）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD5112BCPZ80-500R7DKR
AD5110/AD5112/AD5114
Data Sheet
Rev. B | Page 6 of 28
Parameter
Symbol
Test Conditions/Comments
Min
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
2.3
5.5
V
Logic Supply Range
1.8
VDD
V
Positive Supply Current
IDD
VDD = 5 V
0.75
3.5
A
VDD = 2.7 V
2.5
A
VDD = 2.3 V
2.4
A
EEMEM Store Current3, 6
IDD_NVM_STORE
2
mA
EEMEM Read Current3, 7
IDD_NVM_READ
320
A
Logic Supply Current
ILOGIC
VIH = VLOGIC or VIL = GND
30
nA
Power Dissipation8
PDISS
VIH = VLOGIC or VIL = GND
5
W
Power Supply Rejection3
PSR
VDD/VSS = 5 V ± 10%
RAB = 5 k
43
dB
RAB =10 k
50
dB
RAB = 80 k
64
dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
BW
Code = half scale 3 dB
RAB = 5 k
4
MHz
RAB = 10 k
2
MHz
RAB = 80 k
200
kHz
Total Harmonic Distortion
THD
VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
RAB = 5 k
75
dB
RAB = 10 k
80
dB
RAB = 80 k
85
dB
VW Settling Time
ts
VA = 5 V, VB = 0 V,
±0.5 LSB error band
s
RAB = 5 k
2.5
s
RAB = 10 k
3
s
RAB = 80 k
10
s
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 5 k
7
nV/√Hz
RAB = 10 k
9
nV/√Hz
RAB = 80 k
20
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10
TA = 25°C
1
MCycles
100
kCycles
Data Retention11
50
Years
1 Typical values represent average readings at 25°C, VDD= 5 V, V
SS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at V
WB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 s.
8 P
DISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use V
DD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (T
J) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
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