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參數(shù)資料
| 型號： | AD5112BCPZ80-500R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 64POS 80K 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 80k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.8 V ~ 5 V，2.3 V ~ 5.5V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-UFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-UD（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD5112BCPZ80-500R7DKR |
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Data Sheet
AD5110/AD5112/AD5114
Rev. B | Page 23 of 28
EEPROM WRITE ACKNOWLEGDE POLLING
After each write operation to the EEPROM, an internal write
cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition,
followed by the slave address and the write bit. If the I2C
interface responds with an acknowledge, the write cycle is
complete, and the interface is ready to proceed with further
operations. Otherwise, I2C interface polling can be repeated
until it succeeds.
READ OPERATION
of the RDAC register and EEPROM memory through the I2C
interface by using Command 6 (see Table 10).
the user must first issue a readback command to the device.
This begins with a start command, followed by an address
acknowledges that it is prepared to receive data by pulling
SDA low.
AD5114, the most significant byte followed by the least
significant byte. Both of these data bytes are acknowledged by
bytes contain the read instruction, which enables readback of
the RDAC register, EEPROM memory. The user can then read
back the data. This begins with a start command followed by an
address byte (R/W = 1), after which the device acknowledges
that it is prepared to transmit data by pulling SDA low. Two
bytes of data are then read from the device, which are both
acknowledged by the master, as shown in Figure 45. A stop
condition follows. If the master does not acknowledge the first
byte, then the second byte is not transmitted by the AD5110/
readback.
RESET
Command 4 (see Table 10). The reset command loads the
RDAC register with the contents of the EEPROM and takes
approximately 25 s. EEPROM is pre-loaded to midscale at the
factory, and initial power-up is, accordingly, at midscale.
SHUTDOWN MODE
the software shutdown command, Command 3 (see Table 10).
This feature places the RDAC in a zero-power-consumption
state where Terminal A is open-circuited and the wiper,
Terminal W is connected to Terminal B but a finite wiper
resistance of 45 Ω is present. The part can be taken out of
shutdown mode by executing Command 3 (see Table 10)
and setting Bit DB0 to 0.
SCL
SDA
START BY
MASTER
ACK. BY
AD5110
ACK. BY
AD5110
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 3
LEAST SIGNIFICANT DATA BYTE
SCL (CONTINUED)
SDA (CONTINUED)
ACK. BY
AD5110
STOP BY
MASTER
STOP BY
MASTER
0
1
9
1
9
1
0
1
A1
A0
0
C2
C1
C0
D4
D3
D5
D7
D6
D2
D1
D0
R/W
SCL
SDA
START BY
MASTER
ACK. BY
AD5110
NO ACK.
BY MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE
0
1
9
1
0
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
09582-
045
Figure 45. AD5110 Interface Read Command
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