參數(shù)資料
型號(hào)： AD5100YRQZ
廠商： ANALOG DEVICES INC
元件分類： 電源管理
英文描述： System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
中文描述： 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝： 0.025 INCH PITCH, ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù)： 4/32頁
文件大?。?/td> 495K
代理商： AD5100YRQZ
AD5100
Preliminary Technical Data
Parameter
V
4MON
Threshold Tolerance
(Figure 7 and Table 5a)
V
4MON
Hysteresis
Reset Hold Time Tolerance
(Figures 6, 7, and Table 6a)
V
3,4MON
–to-RESET Delay
RESET Output Voltage
Rev. PrJ | Page 4 of 32
Symbol
Δ
V
4MON
V
4_HYSTERESIS
Δ
t
RS_HOLD
Conditions
T
A
= 25
o
C
T
A
= -40
o
C to 85
o
C
T
A
= -40
o
C to 125
o
C
Does not apply to codes 0x6 and
0x7
V
3MON
≥
4.38V, I
SOURCE
= 120uA
2.7V < V
3MON
≤
4.38V, I
SOURCE
= 30uA
2.3V < V
3MON
≤
2.7V, I
SOURCE
= 20uA
1.8V
≤
V
3MON
≤
2.3V, I
SOURCE
= 8uA
V
3MON
> 4.38V, I
SINK
= 3.2mA
V
3MON
< 4.38V, I
SINK
= 1.2mA
RESET = 0, V
3MON
= 5.5V
Min
-2.5
-3
-3.5
-10
Typ
1
6
Max
+2.5
+3
+3.5
+10
Unit
%
%
%
%
%
t
RS_DELAY
V
OH
V
3MON
-1.5
70
μs
V
RESET Output Short-Circuit
Current
3
Glitch Immune Time
V
4OUT
Maximum Output
V
4OUT
Propagation Delay
V
4OUT
Maximum Frequency
WDI (WATCHDOG INPUT)
WDI Programmable-Timeout
Tolerance
(Figure 8 and Table 6a)
WDI Pulse Width
Watchdog-Initiated RESET Pulse
Width
Watchdog-Initiated SHDN
WDI Input Voltage
WDI Input Current
MR (
MANUAL RESET) INPUT
MR Input Voltage
MR Pulse Width
MR Deglitching
MR -to-Reset Delay
MR Pullup Resistance (internal to
V3MON)
Reset Hold-Time Tolerance
(Figure 9 and Table 6a)
SERIAL INTERFACES
Input Logic High (SCL, SDA)
4
Input Logic Low (SCL, SDA)
Output Logic High (SDA)
V
OL
I
SOURCE
0.8xV
3MON
0.8xV
3MON
0.8xV
3MON
0.4
0.3
800
V
V
V
V
V
μA
t
GLITCH
V
4OUT_MAX
t
V4OUT_Delay
f
V4OUT
RESET = 0, V
3MON
= 3.6V
Open Drain
Apply to RESET disabled only
50
70
10
400
5.5
μA
μs
V
μs
KHz
Δ
t
WD
-10
+10
%
t
WDI
t
WDR
When no WDI
50
t
WD
/50
ns
ms
t
WD_SHDN
V
IL_WD
V
IH_WD
When no WDI activity > 4 t
WD
WDI = V
3MON
, time average
WDI = 0, time average
0.7xV
3MON
-20
1
0.3xV
3MON
160
s
V
V
μA
μA
V
IL_MR
V
IH_MR
t
MR
t
MR_GLITCH
t
MR_DELAY
0.7*V
3MON
1
100
1
50
0.3*V
3MON
V
V
μs
ns
μ
s
K
Ω
Δ
t
RS_HOLD
Do not apply to codes 0x6 and 0x7
-10
+10
%
V
IH
V
IL
V
OH
External Rpull-up = 2.2k
Ω
External Rpull-up = 2.2k
Ω
V
RAIL
= 3.3V, External Rpull-up =
2.2k
Ω
V
RAIL
= 3.3V, External Rpull-up =
2.2k
Ω
2.0
0
3.0
5.5
0.8
3.3
V
V
V
Output Logic Low (SDA)
V
OL
0
0.4
V
Input Capacitance
POWER SUPPLY
Supply Voltage Range
C
I
5
pF
V
1MON
6.0
30
V
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