參數(shù)資料
型號(hào)： AD5100YRQZ
廠商： ANALOG DEVICES INC
元件分類： 電源管理
英文描述： System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
中文描述： 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝： 0.025 INCH PITCH, ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 495K
代理商： AD5100YRQZ
Preliminary Technical Data
AD5100
Rev. PrJ | Page 25 of 32
111 – Never Occur
[7] – Reserved
Notes
1.
2.
3.
Values AD5100 has when shipped from manufacturer’s factory.
V
2MON
must be 0V for Software Power down.
These register bits are set only. To clear them the AD5100 must be power cycled. In some cases the AD5100 may be connected to an I
2
C bus with
lots of activity. Setting these bits is an added means of ensuring any erroneous activity on the bus does not cause AD5100 special functions to
become active.
I2C Serial Interface
Control of the AD5100 is accomplished via an I
2
C compatible
serial bus. The AD5100 is connected to this bus as a slave device
(the AD5100 has no master capabilities).
The AD5100 has a 7-bit slave address. The six MSBs are 010111
and the LSB is determined by the state of the A0 pin. Therefore
when A0 is low, the AD5100 slave address is 01011110 and
0101111 otherwise. Therefore the A0 pin allows the user to
connect two AD5100s to the same I
2
C bus provided the two
devices comply with the configurations shown in Figure 20.
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a
START condition, which is when SDA goes from
high-to-low while SCL is high. The following byte is
the slave address byte, which consists of the 7-bit slave
address followed by an R/W bit which determines
whether data is read from or written to the slave
device
2.
Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an
Acknowledge bit). The transitions on the SDA line
must occur during the low period of SCL and remain
stable during the high period of SCL.
3.
When all data bits have been read or written, a STOP
condition is established by the master. A STOP
condition is defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master
pulls the SDA line high during the 10
th
clock pulse to
establish a STOP condition. In the read mode, the
master issues a no Acknowledge for the 9
th
clock pulse,
(i.e., the SDA line remains high). The master then
brings the SDA line low before the 10
th
clock pulse and
then high during the 10
th
clock pulse to establish a
STOP condition.
For the AD5100, write operations contain either one or two
bytes, while read operations contain one byte. The AD5100
makes use of an
Address Pointer Register
. The Address Pointer
Register does not have and does not require an address, because
it is the register to which the first data byte of every write
operation is written automatically. This data byte is an address
pointer that sets up one of the other registers for the second
byte of the write operation or for a subsequent read operation.
Table 10 shows the structure of the Address Pointer Register.
Bits [6:0] signify the address of the register that is to be written
to or read from. Bit [7] is used when OTP mode is invoked (use
of this bit is explained later in the OTP section), and should be
‘0’ for normal write/read operations.
Table 10
– Address Pointer Register Structure
Bit #
Function
[7]
[6]
AP6
[5]
AP5
[4]
AP4
follows with two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
Address Pointer Register. The second byte is the data to be
written to the internal data register. After each byte the AD5100
acknowledges by pulling the SDA line low during the 9
th
clock
pulse. Figure 21 illustrated this operation.
[3]
AP3
[2]
AP2
[1]
AP1
[0]
AP0
OTP En
Writing Data to AD5100
When writing data to the AD5100, the user begins by writing
an address byte followed by the R/W bit set to ‘0’ The AD5100
will acknowledge (if the correct address byte is used) by pulling
the SDA line low during the 9
th
clock pulse. The user then
SCL
0
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
ADDRESS POINTER BYTE
FRAME 3
DATA BYTE
ACK. BY
AD5100
ACK. BY
AD5100
ACK. BY
AD5100
STOP BY
MASTER
START BY
MASTER
1
0
1
1
AD0
R/W
OTPAP6 AP5 AP4 AP3 AP2 AP1 AP0
D7
D4
D3
D2
D1
D0
03437-0-035
1
D6
D5
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