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參數(shù)資料
| 型號： | AD5066ARUZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| 中文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 309K |
| 代理商： | AD5066ARUZ |
AD5066
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 3 and
Figure 4. V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 5.5 V
Unit
t
11
20
ns min
t
2
10
ns min
t
3
10
ns min
t
4
16.5
ns min
t
5
5
ns min
t
6
5
ns min
t
7
0
ns min
t
8
1.9
us min
t
8
10.5
us min
t
9
16.5
ns min
t
10
0
ns min
t
11
20
ns min
t
12
20
ns min
t
13
10
ns min
t
14
10
ns min
t
15
10.6
us min
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
Rev. PrB | Page 6 of 20
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
2mA
I
OL
2mA
I
OH
V
OH
(MIN)
TO OUTPUT
PIN
C
L
50pF
0
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
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