- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375231 > AD5066ARUZ (ANALOG DEVICES INC) Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP PDF資料下載
參數(shù)資料
| 型號： | AD5066ARUZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| 中文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 309K |
| 代理商： | AD5066ARUZ |
AD5066
Preliminary Technical Data
INPUT SHIFT REGISTER
The AD5066 input shift register is 32 bits wide (see Figure 8).
The first four bits are don’t cares. The next four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 9) and finally the bit
data-word. The data-word comprises of 16-bit input code
followed by 4 don’t care bits for the AD5066 (see Figure 8).
These data bits are transferred to the DAC register on the 32
nd
falling edge of SCLK.
Rev. PrB | Page 14 of 20
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32
nd
falling edge. However, if SYNC is brought high before the
32
nd
falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
Error! Reference
source not found.
).
0
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 8. AD5066 Input Register Content
POWER-ON RESET
The AD5066 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the POR pin
low, the AD5066 output powers up to 0 V; by connecting the
POR pin high, the AD5066 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
POWER-DOWN MODES
The AD5066 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register (refer to
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device. Any or all DACs (DAC
A - DAC D) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 12 for the contents of the input shift register during
power-down/
power-up operation.
When both Bit DB9 and Bit DB8, in the control register are set to
0, the part works normally with its normal power consumption
of
TBD
at 5 V. However, for the three power-down modes, the
supply current falls to
TBD
at 5 V (
TBD
at 3 V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the Dac to a resistor network of
known values. This has the advantage that the output
impedance of the part is known while the part is in power-
down mode. There are three different options. The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output
stage is illustrated in Figure 9.
The bias generator, resistor string, and other associated linear
circuitry are shut down when the power-down mode is activated.
However, the contents of the DAC register are unaffected when
in power-down. The time to exit power-down is typically 2.5 μs
for V
DD
= 5 V and V
DD
= 3 V (see
Error! Reference source not
found.
).
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC Low) or to the value in the
DAC register before powering down (LDAC high).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5066ARUZ-REEL7 | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| AD5066BRUZ-1 | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| AD5066BRUZ-1REEL7 | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| AD515A | Monolithic Precision, Low Power FET-Input Electrometer Op Amp(低功耗FET輸入運(yùn)放) |
| AD5203 | 4-Channel, 64-Position Digital Potentiometer(4通道數(shù)字電位器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5066ARUZ | 制造商:Analog Devices 功能描述:IC DAC 16BIT TSSOP-16 |
| AD5066ARUZ-REEL7 | 功能描述:IC DAC 16BIT 2.7-5.5V QD 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5066BRUZ | 功能描述:IC DAC 16BIT 2.7-5.5V 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5066BRUZ-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| AD5066BRUZ-1REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。