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參數(shù)資料
| 型號： | AD5066 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| 中文描述： | 完全準(zhǔn)確的16緩沖VOUT電源DAC的SPI接口的2.7伏采用TSSOP至5.5 V位 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 309K |
| 代理商： | AD5066 |
Preliminary Technical Data
AD5066
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrB | Page 9 of 20
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1
LDAC
2
SYNC
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Dac B reference input .This is the reference voltage input pin for Dac B.
Dac A reference input .This is the reference voltage input pin for Dac A.
Unbuffered analog output voltage from DAC A.
Unbuffered analog output voltage from DAC C.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V
DD
powers up
the part to midscale.
Dac B reference input .This is the reference voltage input pin for Dac C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Dac A reference input .This is the reference voltage input pin for Dac D.
Unbuffered analog output voltage from DAC D.
Unbuffered analog output voltage from DAC B.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
3
V
DD
4
5
6
7
8
V
REF
B
V
REF
A
V
OUT
A
V
OUT
C
POR
9
10
V
REF
C
CLR
11
12
13
14
15
V
REF
D
V
OUT
D
V
OUT
B
GND
DIN
16
SCLK
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