參數(shù)資料
型號(hào)： AD5066
廠商： Analog Devices, Inc.
英文描述： Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
中文描述： 完全準(zhǔn)確的16緩沖VOUT電源DAC的SPI接口的2.7伏采用TSSOP至5.5 V位
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 309K
代理商： AD5066
AD5066
Preliminary Technical Data
MICROPROCESSOR INTERFACING
AD5066 to Black
fin
ADSP-BF53X Interface
Figure 10 shows a serial interface between the AD5066 and the
Black
fin
ADSP-BF53X
microprocessor. The ADSP-BF53X
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, while TSCLK0 drives the
SCLK of the parts. The SYNC is driven from TFS0.
Rev. PrB | Page 18 of 20
AD5066
1
ADSP-BF53x
1
SYNC
TFS0
DIN
DTOPRI
SCLK
TSCLK0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
0
Figure 10. AD5066 to Black
fin
ADSP-BF53X Interface
AD5066 to 68HC11/68L11 Interface
Figure 11 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
the serial data line of the DAC.
AD5066
1
68HC11/68L11
1
SYNC
PC7
SCLK
SCK
DIN
MOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
0
Figure 11. AD5066 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/ 68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5066 to 80C51/80L51 Interface
Figure 12 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/ 80L51 drives SCLK of the AD5066,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5066, P3.3 is taken low. The 80C51/80L51 transmit data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 output
the serial data in a format that has the LSB first. The AD5066
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
1
0
AD5066
80C51/80L51
1
SYNC
P3.3
SCLK
TxD
DIN
RxD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 12. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
Figure 13 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
AD5025/45/65 on the rising edge of the SCLK.
MICROWIRE
1
CS
SK
SO
AD5066
SYNC
DIN
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
0
Figure 13. AD5066/45/654 to MICROWIRE Interface
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