參數(shù)資料
型號(hào): AD5063BRMZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/20頁(yè)
文件大?。?/td> 0K
描述: IC DAC 16BIT 2.7-5.5V 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
系列: nanoDAC™
設(shè)置時(shí)間: 4µs
位數(shù): 16
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 333k
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
AD5063
Rev. C | Page 17 of
20
USING THE AD5063 WITH A GALVANICALLY
ISOLATED INTERFACE CHIP
In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. iCoupler provides isolation in excess of 2.5 kV.
Because the AD5063 uses a 3-wire serial logic interface, the
ADuM130x family provides an ideal digital solution for the
DAC interface.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range of 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
Figure 38 shows a typical galvanically isolated configuration
using the AD5063. The power supply to the part also needs to
be isolated; this is accomplished by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5063.
VDD
AD5063
ADMu1300
POWER
10F
0.1F
GND
5V
REGULATOR
SCLK
V0A
VOUT
V0B
SYNC
V0C
V1A
V1B
V1C
SCLK
SDI
DATA
DIN
04
76
6-
03
9
Figure 38. AD5063 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5063 should
have separate analog and digital sections, each on its own area
of the board. If the AD5063 is in a system where other devices
require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5063.
The power supply to the AD5063 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), as do common ceramic types of capacitors.
This 0.1 μF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents from internal
logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by a digital ground. Avoid crossover of digital and analog
signals, if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
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