- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8983 > AD5025BRUZ (Analog Devices Inc)IC DAC DUAL 12BIT SPI 14TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD5025BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT SPI 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 5.8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 13.5mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD5025/AD5045/AD5065
Rev. 0 | Page 19 of 28
STANDALONE MODE
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5025/AD5045/AD5065 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. The SYNC line must be brought high
within 30 ns of the 32nd falling edge of SCLK. In either case, it
must be brought high for a minimum of 1.9 μs before the next
write sequence so that a falling edge of SYNC can initiate the next
write sequence. Because the SYNC buffer draws more current
when VIN = VDD than it does when VIN = 0 V, SYNC should be
idled low between write sequences for even lower power
operation of the part. As mentioned previously, however, SYNC
must be brought high again just before the next write sequence.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The input register is reset, and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see Figure 44).
DAISY-CHAINING
For systems that contain several DACs, or where the user wishes to
read back the DAC contents for diagnostic purposes, the SDO
pin can be used to daisy-chain several devices together and
provide serial readback.
The daisy-chain mode is enabled through a software executable
daisy-chain enable (DCEN) command. Command 1000 is
reserved for this DCEN function (see Table 8). The daisy-chain
mode is enabled by setting a bit (DB1) in the DCEN register.
The default setting is standalone mode, where DB1 = 0.
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device.
Table 9. DCEN (Daisy-Chain Enable) Register
DB1
DB0
Description
0
X
Standalone mode (default)
1
X
DCEN mode
The SCLK is continuously applied to the input register when
SYNC is low. If more than 32 clock pulses are applied, the data
ripples out of the input shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multiDAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
If SYNC is taken high before 32N clocks are clocked into the
part, it is considered an invalid frame and the data is discarded.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input register.
The serial clock can be continuous or a gated clock. A continuous
SCLK source can be used only if SYNC can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
In daisy-chain mode, the LDAC pin cannot be tied permanently
low. The LDAC pin must be used in asynchronous LDAC update
mode, as shown in Figure 3. The LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously
update.
SCLK
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
DB31
DB0
SYNC
06
84
4-
01
0
Figure 44. SYNC Interrupt Facility
Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable
MSB
LSB
DB31 to DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
DB1
DB0
X
1
0
X
1/0
X
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
DCEN register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9760ARUZ | IC DAC 10BIT 125MSPS 28-TSSOP |
| AD5667RBRMZ-1 | IC DAC NANO 16BIT DUAL 10-MSOP |
| VE-262-MW-F1 | CONVERTER MOD DC/DC 15V 100W |
| VE-261-MW-F4 | CONVERTER MOD DC/DC 12V 100W |
| VE-261-MW-F3 | CONVERTER MOD DC/DC 12V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5025BRUZ-REEL7 | 功能描述:IC DAC DUAL 12BIT SPI 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD-5028S | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:ADSL LINE TRANSFORMER |
| AD50294 | 制造商:Analog Devices 功能描述: |
| AD50294-1 | 制造商:Analog Devices 功能描述: |
| AD503 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:N-CHANNEL JFET |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。