參數(shù)資料
型號(hào)： AD2S82ALP
廠商： ANALOG DEVICES INC
元件分類： 位置變換器
英文描述： Variable Resolution, Monolithic Resolver-to-Digital Converters
中文描述： SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 207K
代理商： AD2S82ALP
AD2S81A/AD2S82A
REV. B
–5–
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (+V
S
to –V
S
) . . . . . . . . .
±
12 V dc
±
10%
Power Supply Voltage V
L
. . . . . . . . . . . . . . . . . . +5 V dc
±
10%
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms
±
10%
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . .10% (max)
Phase Shift Between Signal and Reference .
±
10 Degrees (max)
Ambient Operating Temperature Range
Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
Industrial (HP, JP, KP, LP) . . . . . . . . . . . .–40
°
C to +85
°
C
PIN FUNCTION DESCRIPTIONS
Mnemonic
REFERENCE I/P
DEMOD I/P
AC ERROR O/P
COS I/P
ANALOG GND
SIGNAL GND
SIN I/P
+V
DB1–DB16
+V
L
ENABLE
Description
Reference Signal Input
Demodulator Input
Ratio Multiplier Output
Cosine Input
Power Ground
Resolver Signal Ground
Sine Input
Positive Power Supply
Parallel Output Data
Logic Power Supply
Logic Hi-Output Data in High Impedance
State Logic Lo Present Data to the Output Latches
Logic Hi-Most Significant Byte to DB1–DB8
Logic Lo-Most Significant Byte to DB1–DB8
Logic Lo Inhibits Data Transfer to Output Latches
Digital Ground
Select Converter Resolution
Logic Lo DB1–DB16 Inputs
Logic Hi DB1–DB16 Outputs
Converter Busy, Data Not Valid While Busy Hi
Logic State Defines Direction of Input Signal Rotation
Positive Pulse when Converter Output Changes from
1s to All 0s or Vice Versa
Negative Power Supply
VCO Input
Integrator Input
INTEGRATOR O/P Integrator Output
DEMOD O/P
Demodulator Output
COMPLEMENT
*
Active Logic Lo
VCO O/P*
VCO Output
BYTE SELECT
INHIBIT
DIGITAL GND
SC1–SC2*
DATA LOAD*
BUSY
DIR
RIPPLE CLK
–V
VCO I/P
INTEGRATOR I/P
*AD2S82A Only.
Bit Weight Table
Binary
Bits (N)
Resolution Degrees
(2
N
)
Minutes
/Bit
Seconds
/Bit
/Bit
0
1
2
3
4
1
2
4
8
360.0
180.0
90.0
45.0
22.5
21600.0
10800.0
5400.0
2700.0
1350.0
1296000.0
648000.0
324000.0
162000.0
81000.0
16
5
6
7
8
9
32
64
128
256
512
11.25
5.625
2.8125
1.40625
0.703125
675.0
337.5
168.75
84.375
42.1875
40500.0
20250.0
10125.0
5062.5
2531.25
10
11
12
13
14
1024
2048
4096
8192
1
16384
0.3515625
0.1757813
0.0878906
0.0439453
0.0219727
21.09375
10.546875
5.273438
2.636719
1.318359
1265.625
632.8125
316.40625
158.20313
79.10156
15
16
17
18
32768
65536
131072
262144
0.0109836
0.0054932
0.0027466
0.0013733
0.659180
0.329590
0.164795
0.082397
39.55078
19.77539
9.88770
4.94385
ABSOLUTE MAXIMUM RATINGS
1
(with respect to GND)
+V
S2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc
+V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V
S
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
Any Logical Input . . . . . . . . . . . . . . . . . . .–0.4 V dc to +V
L
dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V
S
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .860 mW
Operating Temperature
Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
Industrial (HP, JP, KP, LP) . . . . . . . . . . . . .–40
°
C to +85
°
C
Storage Temperature (All Grades) . . . . . . . . .–65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°
C
CAUTION
1. Absolute Maximum Ratings are those values beyond which damage to the
device may occur.
2. Correct polarity voltages must be maintained on the +V
S
and –V
S
pins.
AD2S81A/AD2S82A PIN CONFIGURATIONS
REFERENCE I/P
DEMOD I/P
DEMOD O/P
INTEGRATOR O/P
ANALOG GND
SIN I/P
+V
S
–V
S
RIPPLE CLK
DIR
AC ERROR O/P
COS I/P
INTEGRATOR I/P
VCO I/P
MSB DB1
BUSY
DB2
DIGITAL GND
DB3
DB4
BYTE SELECT
DB5
DB6
+V
L
DB8 LSB
DB7
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD2S81A
INHIBIT
ENABLE
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
PIN 1
TOP VIEW
(Not to Scale)
NC = NO CONNECT
–V
S
RIPPLE CLK
DIR
BUSY
DATA LOAD
COMPLEMENT
SC2
SC1
DIGITAL GND
INHIBIT
NC
SIN O/P
+V
S
NC
MSB DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
D
D
D
D
D
D
L
+
L
E
B
S
D
AD2S82A
S
A
C
A
D
R
D
I
I
V
V
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