參數(shù)資料
型號(hào)： AD2S81A
廠商： Analog Devices, Inc.
英文描述： Variable Resolution, Monolithic Resolver-to-Digital Converters(可變分辨率,單片R/D變換器)
中文描述： 可變分辨率，單片分解到數(shù)字轉(zhuǎn)換器（可變分辨率，單片的R / D變換器）
文件頁數(shù)： 2/16頁
文件大?。?/td> 195K
代理商： AD2S81A
AD2S81A/AD2S82A–SPECIFICATIONS
AD2S81A
Min
AD2S82A
Min
Parameter
SIGNAL INPUTS
Frequency
Voltage Level
Input Bias Current
Input Impedance
Maximum Voltage
Conditions
Typ
Max
Typ
Max
Units
400
1.8
20,000
2.2
150
50
1.8
20,000
2.2
150
Hz
V rms
nA
M
V pk
2.0
60
2.0
60
1.0
1.0
±
8
±
8
REFERENCE INPUT
Frequency
Voltage Level
Input Bias Current
Input Impedance
400
1.0
20,000
8.0
150
50
1.0
20,000
8.0
150
Hz
V pk
nA
M
60
60
1.0
1.0
CONTROL DYNAMICS
Repeatability
Allowable Phase Shift
Tracking Rate
1
+10
1
+10
1040
260
65
16.25
LSB
Degrees
rps
rps
rps
rps
(Signals to Reference)
10 Bits
12 Bits
14 Bits
16 Bits
User Selectable
–10
–10
260
Bandwidth
1
ACCURACY
Angular Accuracy
H
J
K
L
Guaranteed Monotonic
6
22 + 1 LSB
6
8 + 1 LSB
6
4 + 1 LSB
6
2 + 1 LSB
arc min
arc min
arc min
arc min
6
30 + 1 LSB
Monotonicity
Missing Codes (16-Bit Resolution) J, K
4
1
Codes
Code
L
VELOCITY SIGNAL
Linearity
Reversion Error
DC Zero Offset
2
DC Zero Offset Tempco
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
Output Load
Over Full Range
±
1
6
3
±
2
6
±
1
6
3
±
2
6
% FSD
% FSD
mV
μ
V/
°
C
% FSD
V
% rms O/P
k
–22
–22
6
10
±
10.5
1.5
1.0
6
10
±
10.5
1.5
1.0
1 mA Load
Mean Value
±
8
±
9
±
8
±
9
INPUT/OUTPUT PROTECTION
Analog Inputs
Analog Outputs
Overvoltage Protection
Short Circuit O/P Protection
±
8
±
8
±
8
±
8
V
mA
±
5.6
±
10.4
±
5.6
±
10.4
DIGITAL POSITION
Resolution
Output Format
Load
INHIBIT
3
Sense
Time to Stable Data
ENABLE
3
10, 12, 14 and 16
Bidirectional Natural Binary
3
3
LSTTL
Logic LO to Inhibit
600
600
ns
Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State
ENABLE
/Disable Time
BYTE SELECT
3
Sense
Logic HI
35
110
35
110
ns
MS Byte DB1–DB8,
(LS Byte DB9–DB16)
4
LS Byte DB1–DB8,
(LS Byte DB9–DB16)
4
Logic LO
Time to Data Available
SHORT CYCLE INPUTS
4, 5
60
140
60
140
ns
Internally Pulled High
(100 k
) to +V
S
SC1 SC2
0 0
0 1
1 0
1 1
DATA LOAD
4, 5
Sense
10 Bit
12 Bit
14 Bit
16 Bit
Internally Pulled High (100 k
)
to +V
Logic LO Allows
Data to Be Loaded into the
Counters from the Data Lines
150
300
ns
REV. B
–2–
(@ T
A
= +25
8
C, unless otherwise noted)
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