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參數(shù)資料
| 型號： | AD2S1210WDSTZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV R/D VAR REF OSC 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | R/D 轉(zhuǎn)換器 |
| 分辨率（位）： | 10，12，14，16 b |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD2S1210WDSTZRL7DKR |
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AD2S1210
Rev. A | Page 17 of 36
Angular Latency =
×
amplitude
cosine
sine
threshold
LOS
Arc
/
max
cos
2
(5)
The preceding equation is based on the worst-case angular
error, which can be seen by the AD2S1210 before an LOS fault
is indicated. This occurs if one of the resolver input signals,
either sine or cosine, is lost while the remaining signal is at its
peak amplitude, for example, if the sine input is lost while the
input angle is 90°. The worst-case angular latency is twice the
worst-case angular error.
Signal Degradation Detection
The AD2S1210 indicates that a degradation of signal (DOS) has
occurred for two separate conditions.
When either resolver input (sine or cosine) exceeds the
specified DOS sine/cosine threshold. This threshold is
defined by the user and is set by writing to the internal
register, Address 0x89 (see the Register Map section).
When the amplitudes of the input signals, sine and cosine,
mismatch by more than the specified DOS sine/cosine
mismatch threshold. This threshold is defined by the user
and is set by writing to the internal register, Address 0x8A
(see the Register Map section). The AD2S1210 continuously
stores the minimum and maximum magnitude of the moni-
tor signal in internal registers. The difference between the
minimum and maximum is calculated to determine if a
DOS mismatch has occurred. The initial values for the
minimum and maximum internal registers must be defined
by the user, at Address 0x8C and Address 0x8B, respectively
(see the Register Map section).
DOS is indicated by a logic low on the DOS pin. When DOS is
indicated, the output is latched low until the user enters configura-
tion mode and reads the fault register. The DOS condition has
priority over the LOT condition, as shown in Table 6. To deter-
mine the cause of the DOS fault detection, the user must read
the fault register, Address 0xFF (see the Register Map section).
Time Latency for LOS and DOS Detection
Note that the monitor signal is generated on the active edge of
the internal AD2S1210 clock. The internal clock is generated
by dividing the externally applied CLKIN frequency by 2; for
example, when using a CLKIN frequency of 8.192 MHz the
internal AD2S1210 clock is 4.096 MHz. The AD2S1210 conti-
nuously stores the minimum and maximum magnitude of the
monitor signal in internal registers. The values stored in these
internal registers are compared to the LOS and DOS thresholds
configured by the user at set intervals. This interval, known as
the window counter period, is dependent on the excitation
frequency configured by the user. It is set to ensure that two
window counter periods include at least one full period of the
excitation frequency applied to the resolver. The window
counter period is defined in terms of internal clock cycles. The
window counter periods for the range of excitation frequencies
on the AD2S1210 are outlined in Table 5.
Table 5. Window Counter Period vs. Excitation Frequency
Range, CLKIN = 8.192 MHz
Excitation Frequency
Range
Number of
Internal Clock
Cycles
Window
Counter Period
2 kHz ≤ Exc Freq < 4 kHz
1065
260
4 kHz ≤ Exc Freq < 8 kHz
554
135.25
8 kHz ≤ Exc Freq ≤ 20 kHz
256
62.5
1 CLKIN = 8.192 MHz. The window counter period scales with clock frequency
and can be calculated by multiplying the number of internal clock cycles by
the period of the internal clock frequency, that is, CLKIN/2.
The AD2S1210 detects an LOS or DOS due to the resolver inputs
(sine or cosine) falling below or exceeding the LOS and DOS
thresholds within two window counter periods. For example,
with an excitation frequency of 10 kHz, a fault is detected within
125 μs. A persistent fault is detected within one window counter
period of the reading and clearing the fault register.
Note that the time latency to detect the occurrence of a DOS
mismatch fault is dependent on the speed of rotation of the
resolver. The worst-case time latency to detect a DOS mismatch
fault is the time required for one full rotation of the resolver.
Loss of Position Tracking Detection
The AD2S1210 indicates that a loss of tracking (LOT) has
occurred when
The internal error signal of the AD2S1210 has exceeded
the specified angular threshold. This threshold is defined
by the user and is set by writing to the internal register,
Address 0x8D (see the Register Map section).
The input signal exceeds the maximum tracking rate. The
maximum tracking rate depends on the resolution defined
by the user and the CLKIN frequency.
LOT is indicated by a logic low on the LOT pin and is not latched.
LOT has hysteresis and is not cleared until the internal error
signal is less than the value defined in the LOT low threshold
register, Address 0x8E (see the Register Map section).
When the maximum tracking rate is exceeded, LOT is cleared
only if the velocity is less than the maximum tracking rate and
the internal error signal is less than the value defined in the LOT
low threshold register. LOT can be indicated for step changes in
position (such as after a RESET signal is applied to the AD2S1210).
It is also useful as a built-in test to indicate that the tracking
converter is functioning properly. The LOT condition has lower
priority than both the DOS and LOS conditions, as shown in
. The LOT and DOS conditions cannot be indicated using
the LOT and DOS pins at the same time. However, both condi-
tions are indicated separately in the fault register. To determine
the cause of the LOT fault detection, the user must read the fault
register, Address 0xFF (see the
section).
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