參數(shù)資料
型號(hào): AD28MSP01KR
廠商: ANALOG DEVICES INC
元件分類: 調(diào)制器/解調(diào)器
英文描述: PSTN Signal Port
中文描述: MODEM-SUPPORT CIRCUIT, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 20/28頁(yè)
文件大小: 368K
代理商: AD28MSP01KR
AD28msp01
REV. A
–20–
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
Timing Requirement:
F
MCK
t
MCK
t
MKL
t
MKH
MCLK Frequency
MCLK Period
MCLK Width Low
MCLK Width High
13.824
72.34
0.5t
MCK
– 10
0.5t
MCK
– 10
13.824
72.34
0.5t
MCK
+ 10
0.5t
MCK
+ 10
MHz
±
50 ppm
ns
ns
ns
Switching Characteristic:
t
SCK
t
SKL
t
SKH
Control Signals
Timing Requirement:
t
RSP
SCLK Period
SCLK Width Low
SCLK Width High
8t
MCK
– 10
4t
MCK
– 10
4t
MCK
– 10
8t
MCK
+ 10
4t
MCK
+ 10
4t
MCK
+ 10
ns
ns
ns
RESET
Width Low
5t
MCK1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 1000 processor cycles assuming stable CLKIN (not including
crystal oscillator start-up time).
MCLK
SCLK
t
MCK
t
MKL
t
MKH
t
SKH
t
SCK
t
SKL
Figure 16. Clock Signals
Serial Port 3-State
Parameter
Min
Max
Unit
Switching Characteristic:
t
SPD
t
SPE
t
SPV
CS Low to SDO, SDOFS, SCLK Disable
CS High to SDO, SDOFS, SCLK Enable
CS High to SDO, SDOFS, SCLK Valid
20
ns
ns
ns
0
25
CS
t
SPD
t
SPV
t
SPE
SDO
SDOFS
SCLK
Figure 17. Serial Port 3-State
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