參數(shù)資料
型號： AD261BND-4
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： High Speed, Logic Isolator
中文描述： 5 I/O, PIA-GENERAL PURPOSE, PQIP16
封裝： STAGGERED, PLASTIC, DIP-22/16
文件頁數(shù)： 2/6頁
文件大?。?/td> 183K
代理商： AD261BND-4
–2–
REV. 0
AD261–SPECIFICATIONS
(Typical at T
A
= +25
8
C, +5 V dc
SYS
, +5 V dc
FLD
, t
RR
= 50 ns max unless otherwse noted)
Parameter
Conditions
Min
T yp
Max
Units
INPUT CHARACT ERIST ICS
T hreshold Voltage
Positive T ransition (V
T +
)
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
2.0
3.0
0.9
1.2
0.4
0.5
2.7
3.2
1.8
2.2
0.9
1.0
5
0.5
3.15
4.2
2.2
3.0
1.4
1.5
V
V
V
V
V
V
pF
μ
A
Negative T ransition (V
T –
)
Hysteresis Voltage (V
H
)
Input Capacitance (C
IN
)
Input Bias Current (I
IN
)
Per Input
OUT PUT CHARACT ERIST ICS
Output Voltage
1
High Level (V
OH
)
+5 V dc
SYS
= 4.5 V, |I
O
| = 0.02 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 4 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 0.02 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 4 mA
ENABLE
SYS/FLD
@ Logic Low/High Level Respectively
4.4
3.7
V
V
V
V
μ
A
Low Level (V
OL
)
0.1
0.4
Output T hree-State Leakage Current
0.5
DYNAMIC RESPONSE
1
(Refer to Figure 2)
Max Logic Signal Frequency (f
)
Waveform Edge Symmetry Error (t
ERROR
)
Logic Edge Propagation Delay (t
PHL
, t
PLH
)
Minimum Pulsewidth (t
)
Max Output Update Delay on Fault or After
Power-Up Reset Interval (
≈
30
μ
s
)
2
50% Duty Cycle, +5 V dc
SYS
= 5 V
t
PHL
vs. t
PLH
20
MHz
ns
ns
ns
±
1
14
25
25
12
μ
s
ISOLAT ION BARRIER RAT ING
3
Operating Isolation Voltage (V
CMV
)
AD261A
AD261B
AD261A
AD261B
375
1250
V rms
V rms
V rms
V rms
V/
μ
s
pF
μ
A rms
Isolation Rating T est Voltage (V
CMV T EST
)
4
1750
3500
10,000
T ransient Immunity (V
T RANSIENT
)
Isolation Mode Capacitance (C
ISO
)
Capacitive Leakage Current (I
LEAD
)
T otal Capacitance, All Lines
240 V rms @ 60 Hz
9
15
2
POWER SUPPLY
Supply Voltage (+5 V dc
SYS
and +5 V dc
FLD
)
Rated Performance
Operating
Effective, per Input, Either Side
Effective per Output, Either Side—No Load
Each, +5 V dc
SYS & FLD
All Lines @ 10 MHz (Sum of +5 V dc
SYS & FLD
)
4.5
4.0
5.5
5.75
V dc
V dc
pF
pF
mA
mA
Power Dissipation Capacitance
8
28
4
18
Quiescent Supply Current
Supply Current
T EMPERAT URE RANGE
Rated Performance (T
A
)
5
Storage (T
ST G
)
–25
–40
+85
+85
°
C
°
C
NOT ES
1
For best performance, bypass +5 V dc supplies to com., at or near the device (0.01
μ
F). +5 V dc supplies are also internally bypassed with 0.05
μ
F.
2
As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30
μ
s after the point
where +5 V dc
passes above 3.3 V.
3
“Operating” isolation voltage is derived from the Isolation T est Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot”
tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the
same as a hi-pot test (but nondestructive).
4
Partial Discharge at 80 pC T HLD.
5
Supply Current will increase slightly, but otherwise the unit will function within specification to –40
°
C.
Specifications are subject to change without notice.
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