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Class-D Audio Power Amplifier
AD1990/AD1992/AD1994/AD1996
Preliminary Technical Data
FEATURES
Rev. PrA – 1/20/05
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
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Tel: 781.329.4700
Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
www.analog.com
Integrated Stereo Modulator & Power Stage
0.005% THD+N
101.5dB Dynamic Range
PSRR > 65 dB
R
DS-ON
< 0.3
(per transistor)
Efficiency > 80% @ 5W/6
EMI Optimized Modulator
On-Off-Mute Pop Noise Suppression
Short Circuit Protection
Over-Temperature Protection
Low Cost DMOS Process
APPLICATIONS
Flat Panel Televisions
Automotive Amplifiers
PC Audio Systems
Mini Components
GENERAL DESCRIPTION
The AD199x is a two channel Bridge Tied Load (BTL)
switching audio power amplifier with integrated
∑
modulator.
The modulator accepts a 1Vrms input signal (maximum power)
and generates a switching waveform to drive speakers directly.
One of the two modulators can control both output stages
providing twice the current for single-channel applications. A
digital, microcontroller-compatible interface provides control of
reset, mute and PGA gain as well as output signals for thermal
and over-current error conditions. The output stage can operate
from supply voltages ranging from 8V to 20V. The analog
modulator and digital logic operate from a 5V supply.
AD1990: 5Wx2 (10Wx1)
AD199
2
: 10Wx2 (20Wx1)
AD199
4
: 25Wx2 (50Wx1)
AD199
6
: 40Wx2 (80Wx1)
PGND1
Σ
MODULATOR
PGA
LEFT CHANNEL
VOLTAGE
REFERENCE
OSCILLATOR
MODE CONTROL LOGIC
MUTE/
POP
CONTROL
TEMPERATURE
SENSE &
OVER-CURRENT
PROTECTION
19
E
29
M
17
E
30
R
49
M
18
E
7,8
4,5,6
1,2,3
9,10
11,12,13
OUTL-
14,15,16
PGND1
55
27
CLKI
28
CLKO
22
21
20
41,42
PVDD2
43,44,45
OUTR+
46,47,48
PGND2
39,40
PVDD2
36,37,38
OUTR-
33,34,35
PGND2
50
51
60
53
31
32
62
63
PVDD
OUTL+
PGND1
PVDD1
REF_FILT
D
D
D
N
N
N
N
P
P
A
A
AVDD
AGND
DVDD
DGND
57
56
23,26
1
2
1
2
PGND2
PVDD2
PVDD2
PGND2
LEVEL
SHIFT
+
DEAD
TIME
CONTROL
Σ
MODULATOR
PGA
RIGHT CHANNEL
DRIVER
HIGH SIDE
DRIVER
LOW SIDE
DRIVER
HIGH SIDE
DRIVER
LOW SIDE
DRIVER
HIGH SIDE
DRIVER
LOW SIDE
LEVEL
SHIFT
+
DEAD
TIME
CONTROL
Figure 1. Block Diagram