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參數(shù)資料
| 型號： | AD1974 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 4 ADC，具有鎖相環(huán)，192千赫，24位編解碼器 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 307K |
| 代理商： | AD1974 |
AD1974
Rev. 0 | Page 12 of 24
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CIN
0
0
COUT
0
1
CCLK
0
0
CLATCH
0
0
D0
D0
D8
D8
D22
D23
D9
D9
CLATCH
CCLK
CIN
COUT
t
CCH
t
CCL
t
CDS
t
CDH
t
CLS
t
CCP
t
CLH
t
COTS
t
COD
t
COE
0
Figure 5. Format of the SPI Signal
SERIAL CONTROL PORT
The AD1974 has an SPI control port that permits the program-
ming and reading back of the internal control registers for the
ADCs and the clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal MCLK enable, which is set to 1;
ADC BCLK and LRCLK master/slave, which are set by COUT.
Standalone mode only supports stereo mode with an I
2
S data
format and 256 f
S
MCLK rate (see Table 11 for details). Using a
weak pull-up resistor in applications that have a microcontroller
is highly recommended. This pull-up resistor ensures that the
AD1974 recognizes the presence of a microcontroller.
The SPI control port of the AD1974 is a 4-wire serial control
port. The format is similar to that of the Motorola SPI format
except that the input data-word is 24 bits wide. The serial bit
clock and latch can be completely asynchronous to the sample
rate of the ADCs. Figure 5 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1974, the address is 0x04, shifted left one bit due to the R/W
bit. The second byte is the AD1974 register address and the
third byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1974 is designed for 3.3 V supplies. Separate power
supply pins (Pin 5, Pin 13, Pin 33, Pin 37, and Pin 38) are pro-
vided for the analog and digital sections. These pins should be
bypassed with 100 nF ceramic chip capacitors, as close to the
pins as possible, to minimize noise pickup. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be placed
on the same PC board as the codec. For critical applications,
improved performance is obtained with separate supplies for
the analog and digital sections. If this is not possible, it is rec-
ommended that the analog and digital supplies be isolated by
means of a ferrite bead in series with each supply. It is
important that the analog supply be as clean as possible.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC internal voltage reference (VREF) is brought out
on FILTR and should be bypassed as close as possible to the
AD1974 with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
VREF can be disabled in the PLL and Clock Control 1 register
and FILTR can be driven from an external source. The ADC
input gain varies by the inverse ratio.
CM is the internal common-mode reference. It should be
bypassed as close as possible to the AD1974, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The four ADC channels use a common serial bit clock (ABCLK)
and a left-right framing clock (ALRCLK) in the serial data port.
The clock signals are all synchronous with the sample rate. The
normal stereo serial modes are shown in Figure 11.
The ADC serial data modes default to I
2
S. The ports can also be
programmed for left justified, right justified, and TDM modes.
The word width is 24 bits by default and can be programmed
for 16 or 20 bits. The ADC serial formats and serial clock polarity
are programmable according to the ADC Control 1 register.
The ADC serial ports are programmable to become the bus
masters according to the ADC Control 2 register. By default,
both ADC serial ports are in the slave mode.
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