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參數(shù)資料
| 型號(hào)： | AD1970JSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER BTSC W/CODEC 48-LQFP |
| 產(chǎn)品變化通告： | AD1970 Discontinuation 04/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編碼器 |
| 應(yīng)用： | 機(jī)頂盒，視頻播放器，錄音機(jī) |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
AD1970
Rev. 0 | Page 14 of 20
Dialog Enhancement Register
This controls the built-in dialog enhancement algorithm, and
defaults to 0. The maximum setting is 0100000000000000000000
or a twos complement fractional value of 1.0. This algorithm is
intended to solve the problem of playing back high dynamic
range digital audio signals over a television’s built-in speakers. It
provides an amplitude boost to signals that are in the range
where dialog signals are usually found, while at the same time
preventing loud special effects passages from overloading the
speakers or amplifiers.
I2C READ/WRITE DATA FORMATS
The read/write formats of the I2C port are designed to be byte
oriented. This allows for easy programming of common micro-
controller chips. In order to fit into a byte oriented format, 0s
are appended to the data fields in order to extend the data word
to the next multiple of 8 bits. For example, 22-bit words written
to the parameter RAM are appended with two leading zeroes in
order to reach 24 bits (3 bytes). These zero-extended data fields
are appended to a 2-byte field consisting of a read/write bit and
a 10-bit address. The I2C port knows how many data bytes to
expect based on the address received in the first two bytes.
05500-009
R/W
0
SCL
SDA
0
1
0
AD1
AD0
00
01
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
ACK. BY
AD1970
00
01
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
REGISTER
WRITE
I2C
WRITE
D15
D14
D13
D12
D11
D10
D9
D8
ACK. BY
AD1970
FRAME 4
REGISTER DATA UPPER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD1970
STOP BY
MASTER
FRAME 5
REGISTER DATA LOWER BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
R/W
Figure 4. Sample of I2C Write Format (Control Register 1 Write)
05500-008
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 5
REGISTER DATA BYTE
R/W
0
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
0
AD1
AD0
REPEATED START
BY MASTER
FRAME 4
CHIP ADDRESS BYTE
ACK. BY
AD1970
STOP BY
MASTER
I2C
READ
R/W
0
SCL
SDA
0
1
0
AD1
AD0
00
01
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
ACK. BY
AD1970
00
01
00
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
REGISTER
READ
I2C
WRITE
R/W
Figure 5. Sample of I2C Read Format (Control Register 1 Read)
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