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參數(shù)資料
| 型號(hào)： | AD1970JSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER BTSC W/CODEC 48-LQFP |
| 產(chǎn)品變化通告： | AD1970 Discontinuation 04/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編碼器 |
| 應(yīng)用： | 機(jī)頂盒，視頻播放器，錄音機(jī) |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
AD1970
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
AD1970
TOP VIEW
(Not to Scale)
DVDD
1
RESETB
2
DGND
3
DVDD
4
RSVD
5
DGND
GPIO1
GPIO0
XIN
XOUT
36
35
34
33
32
VOUT_OAMP
6
VIN_OAMP
7
AVDD
8
BTSC_OUT
9
AGND 10
VREF 11
FILTCAP 12
VID_PRES
MCLK
PLL_MODE1
PLL_MODE0
NC
31
30
29
28
27
VID_IN
PGND
26
25
AV
DD
13
AGND
14
V
O
UT_
IAMP
L
15
VIN
_
IA
M
P
L
16
V
O
UT_
IAMP
R
17
VIN
_
IA
M
P
R
18
CAP
LP
19
CAP
LN
20
CAP
RP
21
CAP
RN
22
PVD
D
23
PLL_LF
24
DGND
ADR0
ADR1
SC
L
SD
A
48
47
46
45
44
DIG_
IN_
E
N
LRCLK
BCLK
S
DATA
GPIO3
43
42
41
40
39
GPIO2
DV
DD
38
37
05500-002
Figure 2. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
Pin Name
Input/Output
Description
1
DVDD
Digital Power.
2
RESETB
IN
Reset—Active Low. After RESETB transitions from low to high, the AD1970 BTSC encoder
core goes through an initialization sequence where all registers are set to 0. The
initialization is completed after 1024 MCLK cycles. New values should not be written to
the control port until the initialization is complete.
3
DGND
Digital Ground.
4
DVDD
Digital Power. 3.3 V nominal.
5
RSVD
Reserved—Connect to DGND.
6
VOUT_OAMP
OUT
Output voltage of internal op amp to be used for BTSC output low pass filter.
7
VIN_OAMP
IN
Negative input of internal op amp to be used for BTSC output low pass filter.
8
AVDD
Analog Power.
9
BTSC_OUT
OUT
Encoded BTSC Output. The nominal output voltage for a 300 Hz, 0 dB mono input signal is
250 mV rms.
10
AGND
Analog Ground.
11
VREF
OUT
Connection for voltage reference noise reduction capacitor. The nominal VREF voltage is
1.5 V; the analog gain scales directly with the voltage on this pin. Any ac signal on this pin
causes distortion and therefore a large decoupling capacitor should be used to ensure the
voltage on VREF is clean.
12
FILTCAP
OUT
Connection for DAC noise reduction capacitor. A 10 F capacitor should be connected to
this pin to reduce the noise on an internal DAC biasing point to provide the highest
performance. It may not be necessary to connect this pin, depending on the quality of the
layout and grounding used in the application circuit.
13
AVDD
Analog Power. 3.3 V nominal. Bypass capacitors should be placed close to the pins and
connected directly to the analog ground plane.
14
AGND
Analog Ground.
15
VOUT_IAMPL
OUT
Output of internal op amp for left channel input amplifier.
16
VIN_IAMPL
IN
Negative input of internal op amp for left channel input amplifier.
17
VOUT_IAMPR
OUT
Output of internal op amp for right channel input amplifier.
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