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參數(shù)資料
| 型號(hào)： | AD1958YRSRL |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 135K |
| 代理商： | AD1958YRSRL |
REV. 0
AD1958
–7–
CLATCH
CCLK
CDATA
D0
D15
D14
Figure 1. Format of SPI Signal
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
MSB
MSB
LSB
LSB
LEFT-JUSTIFIED MODE—16 TO 24 BITS PER CHANNEL
1
2
S MODE—16 TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT f
S
EXCEPT FOR DSP MODE WHICH IS 2
f
.
3. BCLK FREQUENCY IS NORMALLY 64
LRCLK BUT MAY BE OPERATED IN BURST MODE.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LSB
Figure 2. Stereo Serial Modes
The SPI control port is a 3-wire serial control port. The format
is similar to the Motorola SPI format except the input data word
is 16 bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the PLL system or the
DAC. Figure 1 shows the format of the SPI signal. Note that
the CCLK can be gated or continuous,
CLATCH
should be
low during the 16 active clocks.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1958 is designed for five-volt supplies. Separate power
supply pins are provided for the analog, digital, and PLL sec-
tions.
These pins should be bypassed with 100 nF ceramic
chip capacitors, as close to the pins as possible, to minimize
noise. A bulk aluminum electrolytic capacitor of at least 22
μ
F
should also be provided on the same PC board. For best perfor-
mance it is recommended that the analog supply be separate
from the digital and PLL supply. It is recommended that all
supplies be isolated by ferrite beads in series with each supply. It
is expected that the digital and PLL sections will be run from a
common supply but isolated from one another. It is important
that the analog supply be as clean as possible.
The internal voltage reference is brought out on Pin 21 (FILTR)
and should be bypassed as close as possible to the chip with a
parallel combination of 10
μ
F and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog output signal pins. The current drawn
from the FILTR pin should be limited to less than 50
μ
A.
SERIAL DATA PORTS—DATA FORMAT
The DAC serial data input mode defaults to I
2
S. By changing
Bits 4 and 5 in the DAC control register, the mode can be
changed to RJ, DSP, or LJ. The word width defaults to 24 bits
but can be changed by programming Bits 8 and 9 in the DAC
Control Register.
Figure 2 shows the serial mode formats.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1958YRS | PLL/Multibit DAC |
| AD1958 | PLL/Multibit DAC |
| AD1959YRSRL | PLL/Multibit DAC |
| AD1959 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1959YRS | PLL/Multibit DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1959 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:PLL/Multibit DAC |
| AD1959YRS | 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Bulk 制造商:Analog Devices 功能描述: |
| AD1959YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Tape and Reel |
| AD1959YRSZRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R |
| AD-1962-CV1648-PR.RFL- | 制造商:TE Connectivity 功能描述:AD-1962-CV1648-PR.RFL-ADP 989172-000 |
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