參數(shù)資料
型號(hào)： AD1958YRSRL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： PLL/Multibit DAC
中文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO28
封裝： PLASTIC, SSOP-28
文件頁(yè)數(shù)： 2/8頁(yè)
文件大?。?/td> 135K
代理商： AD1958YRSRL
REV. 0
–2–
AD1958–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
(AVDD, DVDD, PVDD)
Ambient Temperature
Input Clock
Input Signal
5.0 V
25
°
C
12.288 MHz (256
×
f
S
Mode)
996.0938 Hz,
0
dB Full Scale
48 kHz
20 Hz to 20 kHz
24 Bits
100 pF
47 k
2.0 V
0.8 V
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Jitter (MCLK)
Duty Cycle (SCLK0, SCLK1)
1
Duty Cycle (MCLK)
Analog Outputs
Single-Ended Output Range (
±
Full Scale)
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5
×
f
S
to 100 kHz)
V
REF
(FILTR)
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
De-Emphasis Gain Error
24
Bits
105
108
dB
dB
105
109
–96
dB
dB
dB
102
–90
27
MHz
33.8688
12.288
22.5792
110
60
50
50
MHz
MHz
MHz
ps rms
ps rms
%
%
175
100
49
51
3.17
V p-p
pF
dB
V
2
–90
2.39
–5
–0.15
±
2.0
±
0.015
150
–3
–120
±
0.1
–100
+5
+0.15
250
+20
%
dB
ppm/
°
C
mV
dB
Degrees
dB
dB
–25
±
0.1
NOTES
1
In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%.
2
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O
(–40
°
C to +105
°
C )
Min
Typ
Max
Unit
Input Voltage HI (V
IH
)
Input Voltage LO (V
IL
)
Input Leakage (I
IH
@ V
IH
= 2.4 V)
Input Leakage (I
IL
@ V
IL
= 0.8 V)
High Level Output Voltage (V
OH
) I
OH
= 1 mA
Low Level Output Voltage (V
OL
) I
OL
= 1 mA
Input Capacitance
2.0
V
V
μ
A
μ
A
V
V
pF
0.8
10
10
3.5
0.4
20
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
AD1958YRS PLL/Multibit DAC
AD1958 PLL/Multibit DAC
AD1959YRSRL PLL/Multibit DAC
AD1959 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1959YRS PLL/Multibit DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1959 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC
AD1959YRS 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Bulk 制造商:Analog Devices 功能描述:
AD1959YRSRL 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Tape and Reel
AD1959YRSZRL 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R
AD-1962-CV1648-PR.RFL- 制造商:TE Connectivity 功能描述:AD-1962-CV1648-PR.RFL-ADP 989172-000
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