參數資料
型號: AD1893JN
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
中文描述: SPECIALTY CONSUMER CIRCUIT, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數: 6/20頁
文件大?。?/td> 216K
代理商: AD1893JN
AD1893
–6–
REV. A
Output Control Signals
Pin Name
DIP
LQFP
I/O
Description
BKPOL_O 19
25
I
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on
rising.
Serial mode zero control for output port.
Serial mode one control for output port.
MODE0_O 18
MODE1_O 17
24
21
I
I
MODE0_O
0
0
1
1
MODE1_O
0
1
0
1
Left-justified, no MSB delay, L
R
_O clock triggered.
Left-justified, MSB delay, L
R
_O clock triggered.
Right-justified, MSB delayed 16 bit clock periods from L
R
_O transition.
WCLK_O triggered, no MSB delay.
Miscellaneous
Pin Name
DIP
LQFP
I/O
Description
XTAL_O
1
40
O
Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies
(F
S
word rates) from 8 kHz to 56 kHz.
Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies
(F
S
word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator
with an external clock source.
Active LO reset. Set HI for normal chip operation.
Mute output. HI indicates that data is not currently valid due to read and write FIFO
memory pointer overlap. LO indicates normal operation.
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to
MUTE_O. Reset LO for normal operation.
Settle slowly to changes in sample rates. HI: Slow-settling mode (
800 ms). Less sensitive
to sample clock jitter. LO: Fast-settling mode (
200 ms). Some narrow-band noise
modulation may result from jitter on the L
R
clocks. This signal may be asynchronous with
respect to the crystal frequency, and dynamically changed, but is normally pulled up or
pulled down on a static basis.
Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal
operation.
No connect. Reserved. Do not connect.
XTAL_I
2
42
I
RESET
MUTE_O
13
16
14
20
I
O
MUTE_I
15
18
I
SETLSLW 28
38
I
PWRDWN 27
36
I
NC
9, 20
1, 5, 8, 11,
12, 15, 17,
19, 22, 23,
26, 29, 33,
34, 37, 39,
41, 44
Power Supply Connections
Pin Name
DIP
LQFP
I/O
Description
V
DD
GND
7, 22
8, 14, 21
6, 28
7, 16, 27
I
I
Positive digital voltage supply.
Digital ground. Pin 14 (DIP) and Pin 16 (LQFP) need not be decoupled.
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