參數(shù)資料
型號(hào)： AD1893JN
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP28
封裝： 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 216K
代理商： AD1893JN
AD1893
REV. A
–5–
AD1893 PIN LIST
Serial Input Interface
Pin Name
DIP
LQFP I/O
Description
DATA_I
3
43
I
Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per
channel.
Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.
Word clock input for input data. This input is rising edge sensitive. (Not required in L
R
input
data clock triggered modes.)
Left/
right
clock input for input data. Must run continuously.
BCLK_I
WCLK_I
4
5
2
3
I
I
L
R
_I
6
4
I
Serial Output Interface
Pin Name
DIP
LQFP I/O
Description
DATA_O
23
30
O
Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
Bit clock input for output data. Need not run continuously; may be gated or used in a burst
fashion.
Word clock input for output data. This input is rising edge sensitive. (Not required in L
R
output
data clock triggered modes.)
Left/
right
clock input for output data. Must run continuously.
BCLK_O
26
35
I
WCLK_O
25
32
I
L
R
_O
24
31
I
Input Control Signals
Pin Name
DIP
LQFP
I/O Description
BKPOL_I
10
9
I
Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK_I.
MODE0_I
MODE1_I
11
12
10
13
I
I
Serial mode zero control for input port.
Serial mode one control for input port.
MODE0_I
MODE1_I
0
0
0
1
1
0
1
1
Left-justified, no MSB delay, L
R
_I clock triggered.
Left-justified, MSB delay, L
R
_I clock triggered.
Right-justified, MSB delayed 16 bit clock periods from L
R
_I transition.
WCLK
_
I triggered, no MSB delay.
PIN CONFIGURATIONS
DIP
1
2
3
7
8
9
10
11
12
4
5
6
13
14
28
27
26
22
21
20
19
18
17
25
24
23
16
15
SERIAL IN
SERIAL OUT
COEF ROM
MULT
FIFO
CLOCK
TRACKING
ACCUM
XTAL_I
DATA_I
BCLK_I
WCLK_I
V
DD
GND
NC
BKPOL_I
MODE0_I
MODE1_I
GND
RESET
L
R
_I
SETSLW
PWRDWN
BCLK_O
WCLK_O
DATA_O
V
DD
GND
NC
BKPOL_O
MODE0_O
MODE1_O
MUTE_O
MUTE_I
L
R
_O
AD1893
XTAL_O
LQFP
NC = NO CONNECT
NC
WCLK_O
NC
V
DD
GND
DATA_O
NC
BCLK_I
NC
V
DD
GND
WCLK_I
N
D
X
N
S
X
N
M
G
N
M
N
N
P
B
N
M
M
N
N
BKPOL_O
MODE0_O
NC
NC
BKPOL_I
MODE0_I
NC
NC
44
39 38
33
40
AD1893
41
42
28
27
26
43
31
30
29
32
25
24
23
21 22
18
20
19
12 13
15 16 17
14
1
2
6
4
5
3
7
8
11
9
10
36
35 34
N
37
L
R
_I
L
R
_O
R
SERIAL IN
MULT
FIFO
ACCUM
CLOCK
TRACKING
SERIAL OUT
COEF ROM
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參數(shù)描述
AD1893JNZ 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W
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AD1893JSTZ 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AD1893JSTZRL 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AD1895 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter
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