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參數(shù)資料
| 型號： | AD1891 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SamplePort立體聲異步采樣速率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 416K |
| 代理商： | AD1891 |
AD1890/AD1891
REV. 0
–7–
T HE ORY OF OPE RAT ION
T here are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1890 and AD1891 SamplePorts does
not require understanding either model. T his section is included
for those who wish a deeper understanding of their operation.
Interpolation/Decimation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRAT IO) by inserting IRAT IO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). T he frequency domain characteris-
tics of the input signal are unaltered by this operation, except
that the zero-padded sequence is considered to be sampled at a
frequency which is the product of original sampling frequency
multiplied by IRAT IO.
T he zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. T he interpo-
lated output signal has been quantized to a much finer time
scale than the original sequence. T he interpolated sequence is
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). T his resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. T he output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. T here is always some error in the output
sample amplitude due to the fact that the output sampling
switch does not close at a time that exactly corresponds to a
point on the fine time scale of the interpolated sequence. How-
ever, this error can be made arbitrarily small by using a very
large interpolation ratio. T he AD1890/AD1891 SamplePort
ASRCs use an equivalent IRAT IO of 65,536 to provide 16-bit
accuracy (
≈
–96 dB T HD+N) across the 0 to 20 kHz audio
band.
T he number of FIR filter taps and associated coefficients is
approximately 4 million. T he equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1890/AD1891 ASRCs
to reduce the complexity and throughput requirements of the
hardware implied by this interpolation/decimation model.
INPUT
SIGNAL
OUTPUT
SIGNAL
ZERO STUFF
INTERPOLATION
FIR LOW
PASS
FILTER
ZERO ORDER
HOLD
REGISTER
RESAMPLING
DECIMATION
A
B
C
D
E
B
C
D
A
TIME
AMP
Figure 1. Interpolation/Decimation Model—Time Domain View
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| AD1895YRS | 192 kHz Stereo Asynchronous Sample Rate Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1891JN | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Analog Devices 功能描述:SAMPLE RATE CNVRTR 28PDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:IC, 16-BIT CONVERTER IC - Bulk |
| AD1891JP | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:IC, 16-BIT CONVERTER IC - Bulk |
| AD1892 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital Receiver/Rate Converter |
| AD1892JR | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
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