參數(shù)資料
型號(hào)： AD1890JN
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SamplePort Stereo Asynchronous Sample Rate Converters
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP28
封裝： 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 416K
代理商： AD1890JN
AD1890/AD1891
REV. 0
–5–
AD1890/AD1891 PIN LIST
Serial Input Interface
Pin Name Number
I/O
Description
DAT A_I
3
I
Serial input, MSB first, containing two channels of 4- to 20-bits of twos-complement data per
channel. AD1891 ONLY: Maximum of 16 data bits per channel; additional bits ignored.
Bit clock input for input data.
Word clock input for input data. T his input is rising edge sensitive. (Not required in L
R
input data
clock triggered mode [T RGLR_I = HI].)
Left/
right
clock input for input data. Must run continuously.
BCLK _I
WCLK _I
4
5
I
I
L
R
_I
6
I
Serial Output Interface
Pin Name Number
I/O
Description
DAT A_O
23
O
Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
Bit clock input for output data.
Word clock input for output data. T his input is rising edge sensitive. (Not required in L
R
output
data clock triggered mode [T RGLR_O = HI].)
Left/
right
clock input for output data. Must run continuously.
BCLK _O
WCLK _O
26
25
I
I
L
R
_O
24
I
Input Control Signals
Pin Name Number
I/O
Description
BK POL_I
10
I
Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK _I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK _I.
T rigger on L
R
_I. HI: Changes in L
R
_I indicate beginning
1
of valid input data. LO: Rising edge of
WCLK _I indicates beginning of valid input data.
MSB delay. HI: Input data is delayed one BCLK _I after either L
R
_I (T RGLR_I = HI) or WCLK _I
(T RGLR_I = LO) indicates the beginning of valid input data. Included for I
2
S data format
compatibility. LO: No delay.
T RGLR_I
11
I
MSBDLY_I 12
I
NOT E
1
T he beginning of valid data will be delayed by one BLCK _I if MSBDEL_I is selected (HI).
Group Delay
Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
T ransport Delay
T he time interval between when an impulse is applied to the
converters input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). T ransport delay is
independent of frequency.
DE FINIT IONS
Dynamic Range
T he ratio of a near full-scale input signal to the integrated noise
in the passband (0 to
≈
20 kHz), expressed in decibels (dB). Dy-
namic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.
T otal Harmonic Distortion + Noise
T otal Harmonic Distortion plus Noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
相關(guān)PDF資料
PDF描述
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