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參數(shù)資料
| 型號： | AD1888JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CONNECTOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD1888JST |
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REV. 0
–4–
AD1888
Parameter
POWER-DOWN STATES
2
Fully Active
ADC
FRONT DAC
SURROUND DAC
CENTER/LFE DAC
ADC + ALL DACs
Mixer
ADC + Mixer
ALL DACs + Mixer
ADC + ALL DACs + Mixer
Standby
Headphone Standby
PR[K:I]
1
PR[6:0]
1
DV
DD
Typ
AV
DD
Typ
Unit
000
000
000
010
101
111
000
000
111
111
111
000
000 0000
000 0001
000 0010
000 0000
000 0000
000 0011
000 0100
000 0101
000 0110
000 0111
011 1111
100 0000
53
44
46
46
46
12
52
45
31
12
0
52
70
66
61
61
61
33
44
39
14
8
0
65
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
1
PR bits are controlled in Reg. 2Ah and 26h
2
Values presented with V
loaded.
Specifications subject to change without notice.
Parameter
Symbol
Min
Typ
Max
Unit
μ
s
ns
μ
s
μ
s
ns
MHz
ppm
ns
ps
ns
ns
kHz
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
RESET Active Low Pulse Width
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulse Width
SYNC Low Pulse Width
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter
1, 2
BIT_CLK High Pulse Width
BIT_CLK Low Pulse Width
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to RESET Inactive (SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from BIT_CLK Rising
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
1.0
162.8
400,000
1.3
19.5
162.8
12.288
1.0
t
CLK_PERIOD
81.4
750
t
CLK_HIGH
t
CLK_LOW
40
39.7
41.7
41.4
48.0
20.8
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISECLK
t
FALLCLK
t
RISESYNC
t
FALLSYNC
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
t
S2_PDOWN
t
SETUP2RST
t
OFF
4
3
2
2
2
2
2
2
2
2
0
15
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
1.0
25
15
50
15
NOTES
1
Guaranteed but not tested.
2
Output jitter directly dependent on crystal input jitter.
Specifications subject to change without notice.
TIMING PARAMETERS
(Guaranteed over Operating Temperature Range)
Parameter
Min
Typ
Max
Unit
CLOCK SPECIFICATIONS
*
Input Clock Frequency (XTAL Mode or Clock Oscillator)
Input Clock Frequency (Reference Clock Mode)
Input Clock Frequency (USB Clock Mode)
Recommended Clock Duty Cycle
24.576
14.31818
48.000
50
MHz
MHz
MHz
%
40
60
*
Guaranteed but not tested.
Specifications subject to change without notice.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1888JST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 20-Bit 48-Pin LQFP T/R |
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| AD1888JSTZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
| AD1889JS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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