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參數(shù)資料
| 型號： | AD1886A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IR Emitting Diode; Power Dissipation, Pd:50mW; Viewing Angle:45 ; Package/Case:SIP; Operating Temperature Range:-25 C to +85 C; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | AC\u0026#39;97聲卡SoundMAX編解碼器 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 281K |
| 代理商： | AD1886A |
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REV. 0
AD1886A
–20–
SPDIF Control Register (Index 3Ah)
u
u
u
u
N m
u
e
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
A
3 h
l
l
r
n
o
C
F
I
D
P
S
V
X
1
R
S
P
S
0
R
S
P
S
L
C 6
C 5
C 4
C 3
C 2
C 1
C 0
R
P E
Y
P
O
C
U
A D
R
P O
h
0
0
0
0
Note: Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or
subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF
bit in register 2Ah is “0”). This ensures that control and status information startup correctly at the beginning of SPDIF transmission.
PRO
Professional: “1” indicates Professional use of channel status, “0” Consumer.
AUD
Non-Audio: “1” indicates data is non PCM format, “0” data is PCM.
COPY
Copyright: “1” indicates copyright is not asserted, “0” copyright is asserted.
PRE
Preemphasis: “1” indicates filter preemphasis is 50/15
μ
s, “0” preemphasis is none.
CC[6-0]
Category Code: Programmed according to IEC standards, or as appropriate.
L
Generation Level: Programmed according to IEC standards, or as appropriate.
SPSR[1,0]
SPDIF Transmit Sample Rate:
SPSR[1:0] = “00” Transmit Sample Rate = 44.1 kHz.
SPSR[1:0] = “01” Reserved.
SPSR[1:0] = “10” Transmit Sample Rate = 48 kHz.
SPSR[1:0] = “11” Transmit Sample Rate = 32 kHz.
V
Validity: This bit affects the “Validity flag,” bit <28> transmitted in each subframe and enables the SPDIF trans-
mitter to maintain connection during error or mute conditions.
V = 1
Each SPDIF subframe (L + R) has bit <28> set to “1.” This tags both samples as valid.
V = 0
Each SPDIF subframe (L + R) has bit <28> set to “0” for valid data and “1” for invalid data (error condition).
Jack Sense/SPDIF Register (Index 72h)
Note: All register bits are
read
/
write
except for JSI, JS and VWI, which are read only.
JSI
Indicates that Jack Sense pin has generated an interrupt. Must be enabled by JSM bit and remains set until soft-
ware clears JSC bit.
VWI
Indicates Voice Wake Interrupt occurred.
JSM
Jack Sense Mode:
1 = Interrupt Mode (Software intervention required).
0 = Jack Sense Mode ( Hardware asserted Mono/Line Muting).
JSMM
Jack Sense Mono Mute:
Setting this bit enables Jack Sense to mute the Mono output.
JSC
Jack Sense Clear:
Setting this bit clears the Jack Sense interrupt (only needed when JSM = 1).
JSD
Jack Sense Disabled:
Setting this bit disables Jack Sense functionality.
JSLM
Jack Sense Line Mute:
Setting this bit enables Jack Sense to mute the LINE_OUT output.
JSOE
Jack Sense Output Enable:
Setting this bit allows the JS pin to operate as GPIO (output mode only).
JSPD
Jack Sense Pull-up Disable:
Setting this bit disables the internal Jack Sense pull-up.
JSOD
Jack Sense Output Data:
Data on this bit is transferred to the JS pin if JSOE = 1 (otherwise no effect).
SPRZ
1 = SPDIF Return to Zero on under run.
0 = SPDIF Repeat last sample on under run.
SPMIX
1 = SPDIF Transmits output of ADC.
0 = SPDIF Transmits AC-Link Time Slot Data.
e
R g
Nu
N m
e
e
m
a
N
1
D 5
1
D 4
1
D 3
1
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
e
e
D
2
7 h
F
I
D
P
S
/
s
n
e
S
k
c
a
J
X
X
I
M
P
S
D
0
S
J
Z
R
P
S
D
P
S
J
X
E
O
O
S
J
M
L
S
J
S
J D
X
S
J C
M
M
S
J
S
J M
1
W
V
X
X
S
J 1
h
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1886AJST | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD1886AJST-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD1886AJSTZ | 制造商:Rochester Electronics LLC 功能描述: |
| AD1886AJSTZ-RL | 制造商:Analog Devices 功能描述:Audio Codec EOL061109 |
| AD1886JST | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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