參數(shù)資料
型號： AD1886A
廠商： Analog Devices, Inc.
英文描述： IR Emitting Diode; Power Dissipation, Pd:50mW; Viewing Angle:45 ; Package/Case:SIP; Operating Temperature Range:-25 C to +85 C; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： AC\u0026#39;97聲卡SoundMAX編解碼器
文件頁數(shù)： 19/28頁
文件大?。?/td> 281K
代理商： AD1886A
REV. 0
AD1886A
–19–
Extended Audio Status and Control Register (Index 2Ah)
u
u
u
u
N m
u
e
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
A
2 h
l
l
C
/
a
t
S
o
i
d
u
A
d
x
E
X
X
X
X
X
V
C
P
S
X
X
X
X
1
A
S
P
S
0
A
S
P
S
X
F
I
D
P
S
X
R
V A
h
0
0
0
0
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended
audio features.
VRA
Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ
signaling.
SPDIF
SPDIF transmitter subsystem enable/disable bit:
“1” indicates SPDIF is enabled, “0” indicates SPDIF is disabled.
SPSA[1,0]
SPDIF Slot Assignment:
SPSA[1, 0] = 00
SPDIF uses AC-LINK slots 3 and 4.
SPSA[1, 0] = 01
SPDIF uses AC-LINK slots 7 and 8.
SPSA[1, 0] = 10
SPDIF uses AC-LINK slots 6 and 9.
SPSA[1, 0] = 11
Reserved.
SPCV
SPDIF Configuration Valid: (Read Only)
“1” indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is supported.
“0” indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is not supported.
PCM DAC Rate Register (Index 2Ch)
u
u
u
N m
u
u
Re
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
)
h
A
7
h
(
C
2
e
a
R
C
A
D
M
C
P
5
1
R
S
4
1
R
S
3
1
R
S
2
1
R
S
1
1
R
S
0
1
R
S
R
S 9
R
S 8
R
S 7
R
S 6
R
S 5
R
S 4
R
S 3
R
S 2
R
S 1
R
S 0
h
0
8
B
B
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read; otherwise, the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
u
u
u
u
N m
u
e
R g
e
m
a
N
1
D 5
1
D 4
1
D 3
1
D 2
D 1
1
D 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
u
a
f
D
)
h
8
7
(
h
2
3
e
a
R
C
D
A
M
C
P
5
1
R
S
4
1
R
S
3
1
R
S
2
1
R
S
1
1
R
S
0
1
R
S
R
S 9
R
S 8
R
S 7
R
S 6
R
S 5
R
S 4
R
S 3
R
S 2
R
S 1
R
S 0
h
0
8
B
B
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read; otherwise, the closest rate supported is returned.
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