- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373862 > AD1879* (Analog Devices, Inc.) High Performance 16-/18-Bit ## Stereo ADCs PDF資料下載
參數(shù)資料
| 型號： | AD1879* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 16-/18-Bit ## Stereo ADCs |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 628K |
AD1878/AD1879
REV. 0
–9–
between each set of input pins (12 to 13, and 17 to 16) to
complete the input bypassing. T his input bypassing mini-
mizes the RF transmission and reception capability of the
AD1878/AD1879 inputs.
For best performance, do not use a socket with the AD1878/
AD1879. If you must socket the part, use pin clips to keep
the part flush with the board, thus keeping bypassing as
close to the chip as possible.
T he AD1878/AD1879 should be placed on a split ground
plane as illustrated in Figure 5. T he digital ground plane
should be placed under the top end of the package and the
analog ground plane should be placed under the bottom end
of the package as shown in Figure 5. T he split should be be-
tween Pins 7 and 8 and between Pins 21 and 22. T he
ground planes should be tied together at one spot under-
neath the center of the package. T his ground plane tech-
nique also minimizes RF transmission and reception.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LRCK
BCK
S0
DV
DD
64/32
DGND
NC
AV
SS
1
AV
SS
2
AGND
APD
VINR–
VINR+
REFR
WCK
DATA
CLK
S1
DGND
DV
DD
AV
SS
1
AV
DD
2
AV
DD
1
AGND
VINL–
VINL+
REFL
RESET
DIGITAL GROUND
PLANE
ANALOG GROUND
PLANE
Figure 5. AD1878/AD1879 Recommended Ground Plane
Each reference pin (14 and 15) should be bypassed with a
resistor and a capacitor. One end of the resistor should be
placed as close to the package pin as possible, and the trace
to it from the reference pin should be as short and as wide as
possible. K eep this trace away from input pin traces! Cou-
pling between input and reference traces will cause second
harmonic distortion. T he resistor is used to reduce the high
frequency coupling into the references from the board.
Wherever possible, minimize the capacitive load on digital
outputs of the part. T his will reduce the digital spike cur-
rents drawn from the digital supply pins.
How to E xtend SNR
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use mul-
tiple AD1879 channels in parallel with a common analog input.
(T he same technique would work with the AD1878. However,
this would be of little value since using a single AD1879 would
be more effective.) T his technique makes use of the fact that the
noise in independent modulator channels is uncorrelated. T hus
every doubling of the number of AD1879 channels used will im-
prove system dynamic range by 3 dB. T he digital outputs from
the corresponding decimator channels have to be arithmetically
averaged to obtain the improved results in the correct data for-
mat. A digital processor, either general-purpose or DSP, can
easily perform the averaging operation.
Shown below in Figure 6 is a circuit for obtaining a 3 dB im-
provement in dynamic range by using both channels of a single
AD1879 with a mono input. T he minus (–) output from the in-
put buffer is sent to both right and left minus AD1879 inputs;
the plus (+) output from the input buffer is sent to both right
and left plus AD1879 inputs. A stereo implementation would
require using two AD1879s and using the full recommended in-
put structure shown above in Figure 2. Note that a single digital
processor would likely be able to handle the averaging require-
ments for both left and right channels.
PIN 1
0.580 (14.73)
0.485 (12.32)
1
14
15
2
8
0.625 (15.87)
0.600 (15.24)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.125 (3.18)
0.250
(6.35)
MAX
0.022 (0.558)
0.014 (0.356)
0.100
BSC
0.200 (5.05)
0.125 (3.18)
0.070 (1.77)
MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
1.565 (39.70)
1.380 (35.10)
Figure 6. Increasing Dynamic Range by Using Two
AD1879 Channels
DIGIT AL INT E RFACE
Modes of Operation
T he AD1878/AD1879’s flexible serial output port produces
data in twos-complement, MSB-first format. Output signals are
to T T L/CMOS logic levels. T he port is configured by pin selec-
tions. T he AD1879 can operate in either master or slave modes.
Each 16-/18-bit output word of a stereo pair can be formatted
within a 32-bit field as right-justified, as I
2
S-compatible, or at
user-selected positions. T he two 32-bit fields constitute a 64-bit
frame (64-bit mode). T he output can also be truncated to 16
bits and formatted in a 16-bit field with two 16-bit fields in a
32-bit frame (32-bit mode).
T he various mode options are pin-programmed with the S0
Mode Select Pin (3), the S1 Mode Select Pin (25), and the
64/32 Bit Rate Select Pin (4). T he function of these pins is
summarized:
Serial Port Operation Mode
64/
32
S0
S1
64-Bit Master Mode—Word Clock Output
64-Bit Master Mode—Word Clock Input
64-Bit Slave Mode
Reserved
32-Bit Master Mode—Word Clock Out HI
32-Bit Master Mode—Word Clock Ignored
32-Bit Slave Mode
Reserved
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
Serial Port Data T iming Sequences
In the “master modes,” the bit clock (BCK ) and left/right clock
(L
R
CK ) are always outputs, generated internally in the AD1878/
AD1879 from the master clock (CLOCK ) input. T he word
clock (WCK ) may either be an internally generated output or a
user-supplied input, depending on the pin-programmed mode
selected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1881 | SNAPAKMAGNETICCIRCUITBREAKER |
| AD1881A | AC’97 SoundMAX Codec |
| AD1881AJST | AC’97 SoundMAX Codec |
| AD1885 | AC’97 SoundMAX Codec |
| AD1885JST | AC’97 SoundMAX Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1879JD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1881 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundMAX Codec |
| AD1881A | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundMAX Codec |
| AD1881AJST | 制造商:Rochester Electronics LLC 功能描述:AC97 VERSION 2.1 CODEC - Bulk 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:IC CODEC AC'97 VERSION 2.1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。