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參數(shù)資料
| 型號(hào)： | AD1879* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 16-/18-Bit ## Stereo ADCs |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 628K |
AD1878/AD1879
REV. 0
–12–
delayed from a master clock input (CLOCK ) rising edge by
t
DLYCK
as shown in Figure 15. T he MSB of the DAT A output
will be delayed from a falling edge of master clock (CLOCK) by
t
DLYD,MSB
. Subsequent bits of the DAT A output in contrast will
be delayed from a rising edge of master clock (CLOCK ) by
t
DLYD
. (T he MSB is valid one-half CLOCK period less than the
subsequent bits.)
For master modes with word clock (WCK ) inputs, bit clock
(BCK ) and left/ right clock (L
R
CK ) will be delayed from a
master clock input (CLOCK ) rising edge by t
DLYCK
as shown in
Figure 16, the same delay as with word clock output modes.
T he word clock (WCK ) input, however, now has a setup time
requirement, t
WSET
, to the rising edge of master clock (CLOCK
at “W”) and a corresponding hold time, t
WHLD
, from the rising
of the third rising edge of CLOCK (W+3) after the setup edge.
See Figure 16. As in the Master Mode—Word Clock Output
case, the MSB of the DAT A output will be delayed from a fall-
ing edge of master clock (CLOCK ) by t
DLYD,MSB
. Subsequent
bits of the DAT A output in contrast will be delayed from a ris-
ing edge of master clock (CLOCK ) by t
DLYD
.
For slave modes, bit clock (BCK ) and left/right clock (L
R
CK )
will be inputs with setup time, t
SET
, and hold time t
HL D
,
requirements to the falling edges of CLOCK as shown in Fig-
ure 17. Note that both edges of BCK and of L
R
CK have setup
and hold time requirements. Note also that L
R
CK is setup to
the falling edge of the “L” CLOCK , coincident with the CLOCK
edge to which a falling edge of BCK is setup (B+3). L
R
CK ’s
hold time requirements are relative to the falling edge of the
“L + 31” CLOCK edge.
Also available with the AD1878/AD1879 is a 32-bit frame mode
where the 1879’s 18-bit output is truncated to 16-bit words and
for both parts the output packed “tightly” into two 16-bit fields
in the 32-bit frame as shown in Figure 13. Note that the bit
clock (BCK ) and data transmission (DAT A) are operating at
one-half the rate as they would in the 64-bit frame modes. T he
distinction between master and slave modes still holds in the
32-bit frame modes, though the word clock (WCK ) becomes ir-
relevant. If “32-Bit Master Mode With Word Clock Out HI” is
selected, the word clock (WCK ) will stay in a constant HI state.
If “32-Bit Master Mode With Word Clock Ignored” is selected,
the word clock pin (WCK ) will be three-stated and any input to
it is ignored as meaningless. (However, such an input should be
tied off to HI or LO and not left to float.)
In both 32-bit master modes, the left/right clock (L
R
CK ) will be
an output, indicating the difference between the left word/field
and right word/field. In 32-Bit Slave Mode, the left/right clock
(L
R
CK ) is an input.
T iming Parameters
T he AD1878/AD1879 uses its master clock, CLOCK to resyn-
chronize all inputs and outputs. T he discussion above presumed
that most timing parameters are relative to the bit clock, BCK .
T his is approximately true and provides an accurate model of
the sequence of timing events. However, to be more precise, we
have to specify all setup and hold times relative to CLOCK .
T hese are illustrated in Figures 15, 16, and 17.
For master modes with word clock (WCK ) output, bit clock
(BCK ), left/right clock (L
R
CK ), and word clock (WCK ) will be
t
RSET
CLOCK INPUT
RESET
t
RHLD
t
RPLS
MIN 4 CLKS
FOR SYNCH
MIN 1 CLK
MAX 2 CLKS
FOR SYNCH
MIN 4 CLKS
FOR SYNCH
1
2
3
4
126 127 128
LRCK OUTPUT
BCK OUTPUT
Figure 14. AD1878/AD1879
RESET
Clock Timing for Synchronizing Master Mode WCK Output
DATA OUTPUT
BCK OUTPUT (64F
S
)
CLOCK INPUT
LRCK & WCK OUTPUTS
t
DLYD,MSB
PREVIOUS
NEW
MSB
MSB–2
14
15
1
16
MSB–1
17
t
DLYD
t
DLYD
t
DLYCK
t
DLYCK
t
DLYCK
t
DLYCK
ZEROS
Figure 15. AD1878/AD1879 Master Mode Clock Timing: WCK Output
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