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參數(shù)資料
| 型號： | AD1878JD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High Performance 16-/18-Bit Stereo ADCs |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 628K |
| 代理商： | AD1878JD |
AD1878/AD1879
REV. 0
–13–
DATA OUTPUT
BCK OUTPUT (64F
S)
CLOCK INPUT
LRCK OUTPUT
WCK INPUT
PREVIOUS
NEW
1
t
DLYCK
t
WSET
t
WHLD
t
DLYD,MSB
MSB
MSB–2
MSB–1
t
DLYD
t
DLYD
t
DLYCK
t
DLYCK
t
DLYCK
ZEROS
W+1 W+2 W+3
W
Figure 16. AD1878/AD1879 Master Mode Clock Timing: WCK Input
DATA OUTPUT
BCK INPUT (64F
S
)
CLOCK INPUT
LRCK INPUT
WCK INPUT
t
HLD
t
SET
L+1
L
W+1 W+2 W+3
W
t
WSET
t
WHLD
t
DLYD,MSB
MSB
MSB–2
MSB–1
t
DLYD
t
DLYD
t
SET
t
SET
t
HLD
B+1 B+2
B
B+3
L+30 L+31
t
HLD
ZEROS
Figure 17. AD1878/AD1879 Slave Mode Timing
For slave modes, the word clock (WCK ) input has the same
setup time requirement, t
WSET
, to the rising edge of master
clock (CLOCK at “W” ) as in Figure 16 and a corresponding
hold time, t
WHLD
, from the rising edge of CLOCK (W+3) after
the setup edge. T he MSB of the DAT A output will be delayed
from a falling edge of master clock (CLOCK ) by t
DLYD,MSB
.
Subsequent bits of the DAT A output in contrast will be delayed
from a rising edge of master clock (CLOCK ) by t
DLYD
.
Synchronizing Multiple AD1878/AD1879s
Multiple AD1878/AD1879s can be synchronized either by
making all AD1878/AD1879s serial port slaves or by making
one AD1879 the serial port master and all other AD1879s
slaves. T hese two options are illustrated in Figure 18.
As a third alternative, it is possible to synchronize multiple mas-
ters all in Master Mode—Word Clock Output mode. See the
“Reset” discussion above in the “Operating Features” section
for timing considerations.
AD1878/AD1879 to DSP56001 Interface
T he 18-bit AD1878/AD1879 can be interfaced quite simply to
the DSP56001 Digital Signal Processor. Figure 19 illustrates
one method of connection. In this implementation, the AD1878/
AD1879 is configured to operate in 64-Bit Master Mode With
Word Clock Output. T hus, the AD1878/AD1879 is the master
of the serial interface. T he AD1878/AD1879 operates indepen-
dently from the DS
μ
Ps clock. T he DSP56001 serial port is
configured to operate in synchronous mode with the AD1878/
AD1879 connected to its synchronous serial interface (SSI) port.
CLOCK
SOURCE
#1
AD1879
MASTER MODE
CLK
DATA
BCK
WCK
LRCK
#2
AD1879
SLAVE MODE
CLK
DATA
BCK
WCK
LRCK
#N
AD1879
SLAVE MODE
CLK
DATA
BCK
WCK
LRCK
CLOCK
SOURCE
#1
AD1879
SLAVE MODE
CLK
DATA
BCK
WCK
LRCK
#2
AD1879
SLAVE MODE
CLK
DATA
BCK
WCK
LRCK
#N
AD1879
SLAVE MODE
CLK
DATA
BCK
WCK
LRCK
Figure 18. Synchronizing Multiple AD1878/AD1879s
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PDF描述 |
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| AD1879JD | High Performance 16-/18-Bit Stereo ADCs |
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| AD1879 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 16-/18-Bit Stereo ADCs |
| AD1879JD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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