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參數(shù)資料
| 型號(hào)： | AD1878JD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High Performance 16-/18-Bit Stereo ADCs |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 628K |
| 代理商： | AD1878JD |
AD1878/AD1879
REV. 0
–11–
MSB
WCK INPUT
32
1
2
3
14
15
16
17
18
19
20
31
32
1
2
3
14
15
16
17
18
19
20
31
32
1
MSB–1 MSB–2 MSB–3
ZEROS
LSB–1
LSB
ZEROS
LSB
LSB
LSB–1
BCK I/O
LRCK I/O
AD1878
DATA OUTPUT
MSB MSB–1 MSB–2 MSB–3
LEFT DATA
PREVIOUS DATA
RIGHT DATA
Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK
(Master Mode or Slave Mode)
WCK INPUT
32
1
2
3
14
15
16
17
18
19
20
31
32
1
2
3
14
15
16
17
18
19
20
31
32
1
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
ZEROS
LSB–1
LSB
PREVIOUS DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
ZEROS
LSB
LSB
LSB–1
BCK I/O
LRCK I/O
AD1879
DATA OUTPUT
LEFT DATA
RIGHT DATA
Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK
(Master Mode or Slave Mode)
LSB2
LSB2
WCK INPUT
32
1
2
3
16
17
18
19
20
21
22
31
32
ZEROS
BCK I/O
LRCK I/O
1
2
3
31
32
RIGHT DATA
MSB MSB–1
1
AD1879
DATA OUTPUT
MSB MSB–1
ZEROS
LSB–3
LSB–1
LSB
AD1878
DATA OUTPUT
MSB MSB–1
ZEROS
LSB–1
LSB
ZEROS
ZEROS
ZEROS
LSB–3
LSB–1
LSB
MSB MSB–1
ZEROS
LSB–1
LSB
ZEROS
RIGHT DATA
16
17
18
19
20
21
22
LEFT DATA
LEFT DATA
Figure 12. AD1878/AD1879 64-Bit Output Frame Timing with WCK as Input: WCK Hl During 1st BCK
(Master Mode or Slave Mode)
16
1
2
3
4
5
6
15
16
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–3
BCK I/O
LRCK I/O
1
2
3
4
5
6
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
15
16
1
LSB–2
LSB–3 LSB–2
AD1879
DATA OUTPUT
AD1878
DATA OUTPUT
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB1
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB
LSB1
LSB
Figure 13. AD1878/AD1879 32-Bit Output Frame Timing (Master Mode or Slave Mode)
At the other limit, if the word clock (WCK ) is HI during the first
bit clock (BCK ) of the field, then the MSB of the output word
will be valid on the rising edge of the 2nd bit clock (BCK ) as
shown in Figure 12. T he effect is to delay the MSB for one bit
clock cycle into the field, making the output data compatible at
the data format level with the I
2
S data format.
In 64-bit frame modes with word clock (WCK ) as an input, the
relative placement of the word clock (WCK ) input can vary
from 32-bit field to 32-bit field, even within the same 64-bit
frame. For example, within a single 64-bit frame the left word
could be right-justified (by keeping WCK LO) and the right
word could be in an I
2
S-compatible data format (by having
WCK HI at the beginning of the second field).
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