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參數(shù)資料
| 型號： | AD1851 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器) |
| 中文描述： | 16位，16 × Fs的PCM音頻數(shù)模轉(zhuǎn)換器（16位，單片的PCM音頻的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | AD1851 |
AD1851/AD1861
REV. A
–7–
AD1851 DIGIT AL CIRCUIT CONSIDE RAT IONS
AD1851 Input Data
Data is transmitted to the AD1851 in a bit stream composed of
16-bit words with a serial, MSB first format. T hree signals
must be present to achieve proper operation. T hey are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. T he LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 5 illustrates the general signal require-
ments for data transfer to the AD1851.
DATA
CLOCK
LATCH
AAAAAAAAA
S
B
M
L
S
B
Figure 5. Signal Requirements for AD1851
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1851 are both T T L and 5 V
CMOS compatible. T he input requirements illustrated in Fig-
ures 5 and 6 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
T he AD1851 input clock can run at a 12.5 MHz rate. T his
clock rate will allow data transfer rates for 2
3
, 4
3
or 8
3
or
16
3
oversampling reconstructions.
>40ns
>40ns
>30ns
>30ns
>15ns
>40ns
DATA
CLOCK
LATCH
>15ns
>30ns
>80.0ns
>15ns
Figure 6. Timing Relationships of AD1851 Input Signals
AD1861 DIGIT AL CIRCUIT CONSIDE RAT IONS
AD1861 Input Data
Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. T hree signals
must be present to achieve proper operation. T hey are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. T he LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 7 illustrates the general signal require-
ments for data transfer to the AD1861.
DATA
CLOCK
LATCH
AAAAAAAAA
L
S
B
M
S
B
Figure 7. Signal Requirements for AD1861
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1861 are both T T L and 5 V
CMOS compatible. T he input requirements illustrated in Fig-
ures 7 and 8 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
T he AD1861 input clock can run at a 13.5 MHz rate. T his
clock rate will allow data transfer rates for 2
3
, 4
3
or 8
3
or
16
3
oversampling reconstructions.
>40ns
>40ns
>30ns
>30ns
>15ns
>40ns
DATA
CLOCK
LATCH
>15ns
>30ns
>74.1ns
>15ns
Figure 8. Timing Relationships of AD1861 Input Signals
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| AD1892JR | Integrated Digital Receiver/Rate Converter |
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| AD1892 | Integrated Digital Receiver/Rate Converter(數(shù)字音頻接收器/采樣率轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1851N | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 16-bit 16-Pin PDIP Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 16-BIT AUDIO DAC - Bulk 制造商:Analog Devices 功能描述:16BIT DAC PCM AUDIO 1851 DIP16 |
| AD1851N-J | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 16-bit 16-Pin PDIP Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 16-BIT AUDIODAC - Bulk |
| AD1851NZ | 制造商:Rochester Electronics LLC 功能描述:IC, MONO 16-BIT AUDIO DAC - Bulk 制造商:Analog Devices 功能描述:16BIT DAC PCM AUDIO 1851 DIP16 |
| AD1851NZ | 制造商:Analog Devices 功能描述:16BIT DAC PCM AUDIO 1851 DIP16 |
| AD1851NZ-J | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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