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參數(shù)資料
| 型號： | AD1839AEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 674K |
| 代理商： | AD1839AEB |
AD1839A
Parameter
TDM256 MODE (Master, 48 kHz and 96 kHz)
t
TBD
t
FSD
t
TABDD
t
TDDS
t
TDDH
TDM256 MODE (Slave, 48 kHz and 96 kHz)
f
AB
t
TBCH
t
TBCL
t
TFS
t
TFH
t
TBDD
t
TDDS
t
TDDH
TDM512 MODE (Master, 48 kHz)
t
TBD
t
FSD
t
TABDD
t
TDDS
t
TDDH
TDM512 MODE (Slave, 48 kHz)
f
AB
t
TBCH
t
TBCL
t
TFS
t
TFH
t
TBDD
t
TDDS
t
TDDH
AUXILIARY INTERFACE (48 kHz and 96 kHz)
t
AXDS
t
AXDH
t
DXD
f
ABP
Slave Mode
t
AXBH
t
AXBL
t
AXLS
t
AXLH
Master Mode
t
AUXBCLK
t
AUXLRCLK
Rev. B | Page 6 of 24
Min
15
15
256 × f
S
17
17
10
10
15
15
15
15
512 × f
S
17
17
10
10
15
15
15
10
10
10
64 × f
S
15
15
10
10
20
15
Max
40
5
10
15
40
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
From MCLK rising edge
From BCLK rising edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
To BCLK falling edge
From BCLK falling edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
From MCLK rising edge
From BCLK rising edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
To BCLK falling edge
From BCLK falling edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
To AUXBCLK rising edge
From AUXBCLK rising edge
From AUXBCLK falling edge
To AUXBCLK rising edge
From AUXBCLK rising edge
From MCLK rising edge
From AUXBCLK falling edge
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
BCLK Frequency
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
BCLK Frequency
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
AUXBCLK Delay
AUXLRCLK Delay
MCLK
0
t
PDR
t
ML
t
MH
t
MCLK
PD/RST
Figure 2. MCLK and PD/RST Timing
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