參數(shù)資料
型號(hào)： AD1833A
廠(chǎng)商： Analog Devices, Inc.
英文描述： 24-Bit, 192 kHz, DAC
中文描述： 24位，192千赫，數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 687K
代理商： AD1833A
REV. 0
AD1833A
–16–
Packed Mode 128
In Packed Mode 128, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 128 f
S
;
therefore, there are 128 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots: six slots of
20 BCLK and two of 4 BCLK. In this mode, the data length is
restricted to a maximum of 20 bits. The three left channels are
written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLK, and then the three right channels are writ-
ten. The L/
R
CLK defines the left and right data transmission; it
is high for the three left channels and low for the three right channels.
Packed Mode 256
In Packed Mode 256, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 256 f
S
;
therefore, there are 256 BCLK periods in each sample interval, and
each sample interval is broken into eight time slots of 32 BCLK
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on the
falling edge of BCLK with a one BCLK period delay from the
start of the slot. After the three left channels are written, there is
a space of 32 BCLK, and then the three right channels are written.
The
L
/RCLK defines the left and right data transmission; it is
low for the three left channels and high for the three right channels.
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
BLANK SLOT
4 SCLK
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLK
DATA
20-BIT DATA
16-BIT DATA
BCLK
BCLK
–1
–2
–3
–4
–1
–2
–3
–4
+4
+3
+2
+1
MSB
LSB
LSB
MSB
L/
R
CLK
Figure 11. Packed Mode 128
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
20-BIT DATA
24-BIT DATA
16-BIT DATA
BCLK
–1
–2
–3
–4
–1
–2
–3
–4
+8
+7
+6
+5
+4
+3
+2
+1
+4
+3
+2
+1
MSB
LSB
LSB
LSB
MSB
–1
–2
–3
–4
MSB
DATA
BCLK
L
/RCLK
Figure 12. Packed Mode 256
相關(guān)PDF資料
PDF描述
AD1833AAST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST-REEL 24-Bit, 192 kHz, DAC
AD1833AAST-REEL 24-Bit, 192 kHz, DAC
AD1833 Multichannel 24-Bit, 192 kHz, DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1833AAST 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 24BIT DAC SMD 1833 LQFP48
AD1833AAST-REEL 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Tape and Reel
AD1833AASTZ 功能描述:IC DAC AUDIO 24BIT 6CH 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱(chēng):MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD1833AASTZKL1 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD1833AASTZ-REEL 功能描述:IC DAC AUDIO 24BIT 6CH 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類(lèi)型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
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