參數(shù)資料
型號： AD1833A
廠商： Analog Devices, Inc.
英文描述： 24-Bit, 192 kHz, DAC
中文描述： 24位，192千赫，數(shù)模轉(zhuǎn)換器
文件頁數(shù)： 14/20頁
文件大?。?/td> 687K
代理商： AD1833A
REV. 0
AD1833A
–14–
I
2
S Timing
I
2
S timing uses an
L
/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The
L
/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 f
S
is used to clock in the data.
There is a delay of 1 bit clock from the time the
L
/RCLK signal
changes state to the first bit of data on the SDINx lines. The data
is written MSB first and is valid on the rising edge of the bit clock.
Left-Justified Timing
Left-justified (LJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64 f
S
is used
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
MSB
L
/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
MSB
+1
LSB
+2
–2
–1
MSB
Figure 6. I
2
S Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
MSB
+1
LSB
+2
–2
–1
MSB
–1
MSB
Figure 7. Left-Justified Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
LSB
MSB
+1
LSB
+2
–2
–1
MSB
Figure 8. Right-Justified Timing Diagram
to clock in the data. The first bit of data appears on the SDINx
lines when the L/
R
CLK toggles. The data is written MSB first
and is valid on the rising edge of the bit clock.
Right-Justified Timing
Right-justified (RJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64 f
S
is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/
R
CLK toggles. In RJ
mode, the LSB of data is always clocked by the last bit clock
before L/
R
CLK transitions. The data is written MSB first and is
valid on the rising edge of the bit clock.
相關(guān)PDF資料
PDF描述
AD1833AAST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST-REEL 24-Bit, 192 kHz, DAC
AD1833AAST-REEL 24-Bit, 192 kHz, DAC
AD1833 Multichannel 24-Bit, 192 kHz, DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1833AAST 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 24BIT DAC SMD 1833 LQFP48
AD1833AAST-REEL 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC I.C. - Tape and Reel
AD1833AASTZ 功能描述:IC DAC AUDIO 24BIT 6CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD1833AASTZKL1 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD1833AASTZ-REEL 功能描述:IC DAC AUDIO 24BIT 6CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
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