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AD1816A
–38–
REV. A
DM
GPSP
DAC Mute. T his bit mutes the digital DAC output entering the analog mixer.
Game Port Speed Select. Selects the operating speed of the game port.
0
Slow Game Port
1
Fast Game Port
Power-Down 3D. T urns off internal Phat Stereo circuitry.
0
On
1
Off
3D Analog Mixer Bypass. Allows the analog output of the D/A converters to bypass the Phat Stereo Circuit. Enables
ultimate flexibility for mixing and any combination of 3D enhanced analog signals or non-3D enhanced signals with
the DAC output.
0
3D Phat Stereo Enabled for DAC Output
1
3D Phat Stereo Bypassed for DAC Output
Power-Down T ime Base. 1 = timer set to 100 ms, 0 = timer set to 10
μ
s.
Power-down count reload on DSP Port enabled; “1” = Reload count if DSP Port enabled. DSP Port is enabled when
Slot 0 of SDI of the DSP Serial Port Input is Alive (Bit 7 = 1).
Power-down count reload on Digital Activity; “1” = Reload count on Digital Activity. Digital Activity is defined as any
activity on (I
2
S0, I
2
S1, FM or PLAYBACK ).
Power-down count reload on Analog Activity; “1” = Reload count on Analog Activity. Analog Activity is defined as any
analog input unmuted (LINE, CD, SYNT H, MIC, PHONE_IN) or MAST ER VOLUME unmuting.
Power-down count reload on ISA Read; “1” = Reload count on ISA read. ISA Read is defined as a read from any active
logical device inside the AD1816A.
Power-down count reload on ISA Write; “1” = Reload count on ISA write. ISA Write defined as a write to any active
logical device inside the AD1816A.
Chip Power-down
1
Power-Down;
0
Power-Up
For Power-up, software should poll the [SSBASE+0] CRY bit for “1” before writing or reading any logical device.
PD3D
3D
PT B
PDP
PDA
PAA
PIR
PIW
CPD
[45] VE RSION ID
7
DE F AUL T = [0xX X X X ]
2
6
5
4
3
2
1
0
7
6
5
4
3
1
0
VER [15:8]
VER [7:0]
[46] RE SE RVE D
7
DE FAULT = [0x0000]
2
6
5
4
3
2
1
0
7
6
5
4
3
1
0
RES
RES
T est register. Should never be written or read under normal operation.
SB Pro; AdLib Registers
T he AD1816A contains sets of ISA Bus registers (ports) that correspond to those used by the SoundBlaster Pro audio card from
Creative Labs and the AdLib audio card from AdLib Multimedia. T able IX lists the ISA Bus SoundBlaster Pro registers. T able X
lists the ISA Bus AdLib registers. Because the AdLib registers are a subset of those in the SoundBlaster card, you can find complete
information on using both of these registers in the
Developer Kit for SoundBlaster Series, 2nd ed. 1993
, Creative Labs, Inc., 1901
McCarthy Blvd., Milpitas, CA 95035.
T able IX . SoundBlaster Pro ISA Bus Registers
Register Name
Music0: Address (w), Status (r)
Music0: Data (w)
Music1: Address (w)
Music1: Data (w)
Mixer Address (w)
Mixer Data (w)
Reset (w)
Music0: Address (w)
Music0: Data (w)
Input Data (r)
Status (r), Output Data (w)
Status (r)
ISA Bus Address
(SB Base) Relocatable in range 0x100 – 0x3F0
(SB Base+1)
(SB Base+2)
(SB Base+3)
(SB Base+4)
(SB Base+5)
(SB Base+6)
(SB Base+8)
(SB Base+9)
(SB Base+A)
(SB Base+C)
(SB Base+E)