參數(shù)資料
型號(hào)： AD15700
廠商： Analog Devices, Inc.
英文描述： 1 MSPS 16-/14-Bit Analog I/O Port
中文描述： 1 MSPS的16-/14-Bit模擬量I / O端口
文件頁(yè)數(shù)： 28/44頁(yè)
文件大?。?/td> 1100K
代理商： AD15700
REV. A
–28–
AD15700
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4. . .VREF/65536). The control logic
toggles these switches, starting with the MSB first, in order to
bring the comparator back into a balanced condition. After the
completion of this process, the control logic generates the ADC
output code and brings BUSY output low.
Modes of Operation
The ADC features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable for specific
applications.
The warp mode allows the fastest conversion rate up to
1
MSPS.
However, in this mode and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con-
secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. This
mode makes the ADC ideal for applications where both high
accuracy and fast sample rate are required.
The normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode makes
the ADC ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
CONTROL
LOGIC
IND
INC
INB
INA
4R
4R
2R
R
REF
REFGND
INGND
32768C
16384C
MSB
4C
2C
C
LSB
SW
A
C
65536C
SW
B
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
COMP
Figure 7. ADC Simplified Schematic
in this mode is 666 kSPS. When operating at 100 SPS, for
example, it typically consumes only 15
m
W. This feature makes
the ADC ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the ADC offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the ADC is shown in Figure 8 and Table III.
111...101
111...111
111...110
000...000
000...010
000...001
ANALOG INPUT
A
–FS + 0.5LSB
–FS + 1LSB
–FS
+FS – 1.5LSB
+FS – 1LSB
Figure 8. ADC Ideal Transfer Function
Table III. Output Codes and Ideal Input Voltages
Digital Output Code
(Hexadecimal)
Straight Twos
Binary
Complement
Description
Analog Input
Full-Scale Range
Least Significant Bit 305.2
m
V
FSR –1 LSB
Midscale +1 LSB
Midscale
Midscale –1 LSB
–FSR +1 LSB
–FSR
±
10 V
±
5 V
152.6
m
V
4.999847 V
152.6
m
V
0 V
–152.6
m
V
–4.999847 V –2.499924 V 152.6
m
V
–5 V
–2.5 V
±
2.5 V
76.3
m
V
2.499924 V
76.3
m
V
0 V
–76.3
m
V
0 V to 10 V
152.6
m
V
9.999847 V 4.999924 V 2.499962 V
5.000153 V 2.570076 V 1.257038 V
5 V
2.5 V
4.999847 V 2.499924 V 1.249962 V
76.3
m
V
0 V
0 V
0 V to 5 V
76.3
m
V
0 V to 2.5 V
38.15
m
V
9.999695 V
305.2
m
V
0 V
–305.2
m
V
–9.999695 V
–10 V
FFFF
1
8001
8000
7FFF
0001
0000
2
7FFF
1
0001
0000
FFFF
8001
8000
2
1.25 V
38.15
m
V
0 V
NOTES
1
This is also the code for an overrange analog input.
2
This is also the code for an underrange analog input.
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